re PR target/89902 (ICE: in extract_insn, at recog.c:2310: unrecognizable insn with -mavx512bitalg)
PR target/89902 PR target/89903 * config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Return false for variable DImode shifts. (dimode_scalar_chain::compute_convert_gain): Do not handle register count operand in variable DImode shifts. (dimode_scalar_chain::make_vector_copies): Remove support to copy count argument of a variable shift instruction to a vector register. (dimode_scalar_chain::convert_reg): Remove support to convert count argument of a variable shift instruction. testsuite/ChangeLog: PR target/89902 PR target/89903 * gcc.target/i386/pr70799-4.c: Remove. * gcc.target/i386/pr70799-5.c: Remove. * gcc.target/i386/pr89902.c: New test. * gcc.target/i386/pr89903.c: Ditto. From-SVN: r270102
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
6fb8055edd
commit
f401d62362
@ -1,3 +1,16 @@
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2019-04-02 Uroš Bizjak <ubizjak@gmail.com>
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PR target/89902
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PR target/89903
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* config/i386/i386.c (dimode_scalar_to_vector_candidate_p):
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Return false for variable DImode shifts.
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(dimode_scalar_chain::compute_convert_gain): Do not handle
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register count operand in variable DImode shifts.
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(dimode_scalar_chain::make_vector_copies): Remove support to copy
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count argument of a variable shift instruction to a vector register.
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(dimode_scalar_chain::convert_reg): Remove support to convert
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count argument of a variable shift instruction.
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2019-04-02 Andrey Belevantsev <abel@ispras.ru>
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PR rtl-optimization/84206
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@ -1058,16 +1058,8 @@ dimode_scalar_to_vector_candidate_p (rtx_insn *insn)
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case ASHIFT:
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case LSHIFTRT:
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if (!REG_P (XEXP (src, 1))
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&& (!SUBREG_P (XEXP (src, 1))
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|| SUBREG_BYTE (XEXP (src, 1)) != 0
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|| !REG_P (SUBREG_REG (XEXP (src, 1))))
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&& (!CONST_INT_P (XEXP (src, 1))
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|| !IN_RANGE (INTVAL (XEXP (src, 1)), 0, 63)))
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return false;
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if (GET_MODE (XEXP (src, 1)) != QImode
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&& !CONST_INT_P (XEXP (src, 1)))
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if (!CONST_INT_P (XEXP (src, 1))
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|| !IN_RANGE (INTVAL (XEXP (src, 1)), 0, 63))
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return false;
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break;
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@ -1664,15 +1656,10 @@ dimode_scalar_chain::compute_convert_gain ()
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{
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if (CONST_INT_P (XEXP (src, 0)))
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gain -= vector_const_cost (XEXP (src, 0));
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if (CONST_INT_P (XEXP (src, 1)))
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{
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gain += ix86_cost->shift_const;
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if (INTVAL (XEXP (src, 1)) >= 32)
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gain -= COSTS_N_INSNS (1);
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}
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else
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/* Additional gain for omitting two CMOVs. */
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gain += ix86_cost->shift_var + COSTS_N_INSNS (2);
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gain += ix86_cost->shift_const;
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if (INTVAL (XEXP (src, 1)) >= 32)
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gain -= COSTS_N_INSNS (1);
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}
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else if (GET_CODE (src) == PLUS
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|| GET_CODE (src) == MINUS
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@ -1788,60 +1775,14 @@ dimode_scalar_chain::make_vector_copies (unsigned regno)
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{
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rtx reg = regno_reg_rtx[regno];
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rtx vreg = gen_reg_rtx (DImode);
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bool count_reg = false;
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df_ref ref;
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for (ref = DF_REG_DEF_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
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if (!bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
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{
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df_ref use;
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/* Detect the count register of a shift instruction. */
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for (use = DF_REG_USE_CHAIN (regno); use; use = DF_REF_NEXT_REG (use))
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if (bitmap_bit_p (insns, DF_REF_INSN_UID (use)))
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{
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rtx_insn *insn = DF_REF_INSN (use);
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rtx def_set = single_set (insn);
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gcc_assert (def_set);
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rtx src = SET_SRC (def_set);
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if ((GET_CODE (src) == ASHIFT
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|| GET_CODE (src) == ASHIFTRT
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|| GET_CODE (src) == LSHIFTRT)
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&& !CONST_INT_P (XEXP (src, 1))
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&& reg_or_subregno (XEXP (src, 1)) == regno)
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count_reg = true;
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}
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start_sequence ();
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if (count_reg)
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{
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rtx qreg = gen_lowpart (QImode, reg);
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rtx tmp = gen_reg_rtx (SImode);
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if (TARGET_ZERO_EXTEND_WITH_AND
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&& optimize_function_for_speed_p (cfun))
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{
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emit_move_insn (tmp, const0_rtx);
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emit_insn (gen_movstrictqi
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(gen_lowpart (QImode, tmp), qreg));
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}
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else
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emit_insn (gen_rtx_SET
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(tmp, gen_rtx_ZERO_EXTEND (SImode, qreg)));
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if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
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{
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rtx slot = assign_386_stack_local (SImode, SLOT_STV_TEMP);
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emit_move_insn (slot, tmp);
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tmp = copy_rtx (slot);
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}
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emit_insn (gen_zero_extendsidi2 (vreg, tmp));
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}
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else if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
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if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
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{
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rtx tmp = assign_386_stack_local (DImode, SLOT_STV_TEMP);
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emit_move_insn (adjust_address (tmp, SImode, 0),
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@ -1889,25 +1830,8 @@ dimode_scalar_chain::make_vector_copies (unsigned regno)
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if (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
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{
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rtx_insn *insn = DF_REF_INSN (ref);
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if (count_reg)
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{
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rtx def_set = single_set (insn);
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gcc_assert (def_set);
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rtx src = SET_SRC (def_set);
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if ((GET_CODE (src) == ASHIFT
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|| GET_CODE (src) == ASHIFTRT
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|| GET_CODE (src) == LSHIFTRT)
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&& !CONST_INT_P (XEXP (src, 1))
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&& reg_or_subregno (XEXP (src, 1)) == regno)
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{
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XEXP (src, 0) = replace_with_subreg (XEXP (src, 0), reg, reg);
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XEXP (src, 1) = vreg;
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}
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}
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else
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replace_with_subreg_in_insn (insn, reg, vreg);
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replace_with_subreg_in_insn (insn, reg, vreg);
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if (dump_file)
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fprintf (dump_file, " Replaced r%d with r%d in insn %d\n",
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@ -2010,43 +1934,7 @@ dimode_scalar_chain::convert_reg (unsigned regno)
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rtx src = SET_SRC (def_set);
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rtx dst = SET_DEST (def_set);
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if ((GET_CODE (src) == ASHIFT
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|| GET_CODE (src) == ASHIFTRT
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|| GET_CODE (src) == LSHIFTRT)
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&& !CONST_INT_P (XEXP (src, 1))
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&& reg_or_subregno (XEXP (src, 1)) == regno)
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{
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rtx tmp2 = gen_reg_rtx (V2DImode);
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start_sequence ();
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if (TARGET_SSE4_1)
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emit_insn (gen_sse4_1_zero_extendv2qiv2di2
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(tmp2, gen_rtx_SUBREG (V16QImode, reg, 0)));
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else
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{
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rtx vec_cst
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= gen_rtx_CONST_VECTOR (V2DImode,
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gen_rtvec (2, GEN_INT (0xff),
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const0_rtx));
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vec_cst
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= validize_mem (force_const_mem (V2DImode, vec_cst));
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emit_insn (gen_rtx_SET
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(tmp2,
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gen_rtx_AND (V2DImode,
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gen_rtx_SUBREG (V2DImode, reg, 0),
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vec_cst)));
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}
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rtx_insn *seq = get_insns ();
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end_sequence ();
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emit_insn_before (seq, insn);
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XEXP (src, 0) = replace_with_subreg (XEXP (src, 0), reg, reg);
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XEXP (src, 1) = gen_rtx_SUBREG (DImode, tmp2, 0);
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}
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else if (!MEM_P (dst) || !REG_P (src))
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if (!MEM_P (dst) || !REG_P (src))
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replace_with_subreg_in_insn (insn, reg, reg);
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bitmap_clear_bit (conv, INSN_UID (insn));
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@ -1,3 +1,12 @@
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2019-04-02 Uroš Bizjak <ubizjak@gmail.com>
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PR target/89902
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PR target/89903
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* gcc.target/i386/pr70799-4.c: Remove.
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* gcc.target/i386/pr70799-5.c: Remove.
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* gcc.target/i386/pr89902.c: New test.
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* gcc.target/i386/pr89903.c: Ditto.
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2019-04-02 Andrey Belevantsev <abel@ispras.ru>
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PR rtl-optimization/84206
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@ -1,17 +0,0 @@
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/* PR target/pr70799 */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -march=slm -mno-stackrealign" } */
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/* { dg-final { scan-assembler "psllq" } } */
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/* { dg-final { scan-assembler "psrlq" } } */
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unsigned long long a, b;
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void test1 (int c)
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{
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a = b << c;
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}
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void test2 (int c)
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{
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a = b >> c;
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}
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@ -1,17 +0,0 @@
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/* PR target/pr70799 */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -march=slm -mavx512vl -mno-stackrealign" } */
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/* { dg-final { scan-assembler "psllq" } } */
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/* { dg-final { scan-assembler "psraq" } } */
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long long a, b;
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void test1 (int c)
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{
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a = b << c;
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}
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void test2 (int c)
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{
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a = b >> c;
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}
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13
gcc/testsuite/gcc.target/i386/pr89902.c
Normal file
13
gcc/testsuite/gcc.target/i386/pr89902.c
Normal file
@ -0,0 +1,13 @@
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/* PR target/89902 */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -fno-tree-coalesce-vars -mavx512bitalg" } */
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void bar (void);
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int
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foo (long long x)
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{
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x <<= (char) x;
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bar ();
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return x;
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}
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14
gcc/testsuite/gcc.target/i386/pr89903.c
Normal file
14
gcc/testsuite/gcc.target/i386/pr89903.c
Normal file
@ -0,0 +1,14 @@
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/* PR target/89903 */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -march=skylake" } */
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int a, b;
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void
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foo (void)
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{
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unsigned long long d = 983040;
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d += a;
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d >>= (short) d;
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b = d;
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}
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