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re PR target/89902 (ICE: in extract_insn, at recog.c:2310: unrecognizable insn with -mavx512bitalg)

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PR target/89902
	PR target/89903
	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p):
	Return false for variable DImode shifts.
	(dimode_scalar_chain::compute_convert_gain): Do not handle
	register count operand in variable DImode shifts.
	(dimode_scalar_chain::make_vector_copies): Remove support to copy
	count argument of a variable shift instruction to a vector register.
	(dimode_scalar_chain::convert_reg): Remove support to convert
	count argument of a variable shift instruction.

testsuite/ChangeLog:

	PR target/89902
	PR target/89903
	* gcc.target/i386/pr70799-4.c: Remove.
	* gcc.target/i386/pr70799-5.c: Remove.
	* gcc.target/i386/pr89902.c: New test.
	* gcc.target/i386/pr89903.c: Ditto.

From-SVN: r270102
This commit is contained in:
Uros Bizjak 2019-04-02 19:05:59 +02:00 committed by Uros Bizjak
parent 6fb8055edd
commit f401d62362
7 changed files with 58 additions and 155 deletions
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13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2019-04-02 Uroš Bizjak <ubizjak@gmail.com>
PR target/89902
PR target/89903
* config/i386/i386.c (dimode_scalar_to_vector_candidate_p):
Return false for variable DImode shifts.
(dimode_scalar_chain::compute_convert_gain): Do not handle
register count operand in variable DImode shifts.
(dimode_scalar_chain::make_vector_copies): Remove support to copy
count argument of a variable shift instruction to a vector register.
(dimode_scalar_chain::convert_reg): Remove support to convert
count argument of a variable shift instruction.
2019-04-02 Andrey Belevantsev <abel@ispras.ru> 2019-04-02 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/84206 PR rtl-optimization/84206

130
gcc/config/i386/i386.c
View File

@ -1058,16 +1058,8 @@ dimode_scalar_to_vector_candidate_p (rtx_insn *insn)
case ASHIFT: case ASHIFT:
case LSHIFTRT: case LSHIFTRT:
if (!REG_P (XEXP (src, 1)) if (!CONST_INT_P (XEXP (src, 1))
&& (!SUBREG_P (XEXP (src, 1)) || !IN_RANGE (INTVAL (XEXP (src, 1)), 0, 63))
|| SUBREG_BYTE (XEXP (src, 1)) != 0
|| !REG_P (SUBREG_REG (XEXP (src, 1))))
&& (!CONST_INT_P (XEXP (src, 1))
|| !IN_RANGE (INTVAL (XEXP (src, 1)), 0, 63)))
return false;
if (GET_MODE (XEXP (src, 1)) != QImode
&& !CONST_INT_P (XEXP (src, 1)))
return false; return false;
break; break;
@ -1664,15 +1656,10 @@ dimode_scalar_chain::compute_convert_gain ()
{ {
if (CONST_INT_P (XEXP (src, 0))) if (CONST_INT_P (XEXP (src, 0)))
gain -= vector_const_cost (XEXP (src, 0)); gain -= vector_const_cost (XEXP (src, 0));
if (CONST_INT_P (XEXP (src, 1)))
{ gain += ix86_cost->shift_const;
gain += ix86_cost->shift_const; if (INTVAL (XEXP (src, 1)) >= 32)
if (INTVAL (XEXP (src, 1)) >= 32) gain -= COSTS_N_INSNS (1);
gain -= COSTS_N_INSNS (1);
}
else
/* Additional gain for omitting two CMOVs. */
gain += ix86_cost->shift_var + COSTS_N_INSNS (2);
} }
else if (GET_CODE (src) == PLUS else if (GET_CODE (src) == PLUS
|| GET_CODE (src) == MINUS || GET_CODE (src) == MINUS
@ -1788,60 +1775,14 @@ dimode_scalar_chain::make_vector_copies (unsigned regno)
{ {
rtx reg = regno_reg_rtx[regno]; rtx reg = regno_reg_rtx[regno];
rtx vreg = gen_reg_rtx (DImode); rtx vreg = gen_reg_rtx (DImode);
bool count_reg = false;
df_ref ref; df_ref ref;
for (ref = DF_REG_DEF_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref)) for (ref = DF_REG_DEF_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
if (!bitmap_bit_p (insns, DF_REF_INSN_UID (ref))) if (!bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
{ {
df_ref use;
/* Detect the count register of a shift instruction. */
for (use = DF_REG_USE_CHAIN (regno); use; use = DF_REF_NEXT_REG (use))
if (bitmap_bit_p (insns, DF_REF_INSN_UID (use)))
{
rtx_insn *insn = DF_REF_INSN (use);
rtx def_set = single_set (insn);
gcc_assert (def_set);
rtx src = SET_SRC (def_set);
if ((GET_CODE (src) == ASHIFT
|| GET_CODE (src) == ASHIFTRT
|| GET_CODE (src) == LSHIFTRT)
&& !CONST_INT_P (XEXP (src, 1))
&& reg_or_subregno (XEXP (src, 1)) == regno)
count_reg = true;
}
start_sequence (); start_sequence ();
if (count_reg)
{
rtx qreg = gen_lowpart (QImode, reg);
rtx tmp = gen_reg_rtx (SImode);
if (TARGET_ZERO_EXTEND_WITH_AND if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
&& optimize_function_for_speed_p (cfun))
{
emit_move_insn (tmp, const0_rtx);
emit_insn (gen_movstrictqi
(gen_lowpart (QImode, tmp), qreg));
}
else
emit_insn (gen_rtx_SET
(tmp, gen_rtx_ZERO_EXTEND (SImode, qreg)));
if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
{
rtx slot = assign_386_stack_local (SImode, SLOT_STV_TEMP);
emit_move_insn (slot, tmp);
tmp = copy_rtx (slot);
}
emit_insn (gen_zero_extendsidi2 (vreg, tmp));
}
else if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
{ {
rtx tmp = assign_386_stack_local (DImode, SLOT_STV_TEMP); rtx tmp = assign_386_stack_local (DImode, SLOT_STV_TEMP);
emit_move_insn (adjust_address (tmp, SImode, 0), emit_move_insn (adjust_address (tmp, SImode, 0),
@ -1889,25 +1830,8 @@ dimode_scalar_chain::make_vector_copies (unsigned regno)
if (bitmap_bit_p (insns, DF_REF_INSN_UID (ref))) if (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
{ {
rtx_insn *insn = DF_REF_INSN (ref); rtx_insn *insn = DF_REF_INSN (ref);
if (count_reg)
{
rtx def_set = single_set (insn);
gcc_assert (def_set);
rtx src = SET_SRC (def_set); replace_with_subreg_in_insn (insn, reg, vreg);
if ((GET_CODE (src) == ASHIFT
|| GET_CODE (src) == ASHIFTRT
|| GET_CODE (src) == LSHIFTRT)
&& !CONST_INT_P (XEXP (src, 1))
&& reg_or_subregno (XEXP (src, 1)) == regno)
{
XEXP (src, 0) = replace_with_subreg (XEXP (src, 0), reg, reg);
XEXP (src, 1) = vreg;
}
}
else
replace_with_subreg_in_insn (insn, reg, vreg);
if (dump_file) if (dump_file)
fprintf (dump_file, " Replaced r%d with r%d in insn %d\n", fprintf (dump_file, " Replaced r%d with r%d in insn %d\n",
@ -2010,43 +1934,7 @@ dimode_scalar_chain::convert_reg (unsigned regno)
rtx src = SET_SRC (def_set); rtx src = SET_SRC (def_set);
rtx dst = SET_DEST (def_set); rtx dst = SET_DEST (def_set);
if ((GET_CODE (src) == ASHIFT if (!MEM_P (dst) || !REG_P (src))
|| GET_CODE (src) == ASHIFTRT
|| GET_CODE (src) == LSHIFTRT)
&& !CONST_INT_P (XEXP (src, 1))
&& reg_or_subregno (XEXP (src, 1)) == regno)
{
rtx tmp2 = gen_reg_rtx (V2DImode);
start_sequence ();
if (TARGET_SSE4_1)
emit_insn (gen_sse4_1_zero_extendv2qiv2di2
(tmp2, gen_rtx_SUBREG (V16QImode, reg, 0)));
else
{
rtx vec_cst
= gen_rtx_CONST_VECTOR (V2DImode,
gen_rtvec (2, GEN_INT (0xff),
const0_rtx));
vec_cst
= validize_mem (force_const_mem (V2DImode, vec_cst));
emit_insn (gen_rtx_SET
(tmp2,
gen_rtx_AND (V2DImode,
gen_rtx_SUBREG (V2DImode, reg, 0),
vec_cst)));
}
rtx_insn *seq = get_insns ();
end_sequence ();
emit_insn_before (seq, insn);
XEXP (src, 0) = replace_with_subreg (XEXP (src, 0), reg, reg);
XEXP (src, 1) = gen_rtx_SUBREG (DImode, tmp2, 0);
}
else if (!MEM_P (dst) || !REG_P (src))
replace_with_subreg_in_insn (insn, reg, reg); replace_with_subreg_in_insn (insn, reg, reg);
bitmap_clear_bit (conv, INSN_UID (insn)); bitmap_clear_bit (conv, INSN_UID (insn));

9
gcc/testsuite/ChangeLog
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@ -1,3 +1,12 @@
2019-04-02 Uroš Bizjak <ubizjak@gmail.com>
PR target/89902
PR target/89903
* gcc.target/i386/pr70799-4.c: Remove.
* gcc.target/i386/pr70799-5.c: Remove.
* gcc.target/i386/pr89902.c: New test.
* gcc.target/i386/pr89903.c: Ditto.
2019-04-02 Andrey Belevantsev <abel@ispras.ru> 2019-04-02 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/84206 PR rtl-optimization/84206

17
gcc/testsuite/gcc.target/i386/pr70799-4.c
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@ -1,17 +0,0 @@
/* PR target/pr70799 */
/* { dg-do compile { target ia32 } } */
/* { dg-options "-O2 -march=slm -mno-stackrealign" } */
/* { dg-final { scan-assembler "psllq" } } */
/* { dg-final { scan-assembler "psrlq" } } */
unsigned long long a, b;
void test1 (int c)
{
a = b << c;
}
void test2 (int c)
{
a = b >> c;
}

17
gcc/testsuite/gcc.target/i386/pr70799-5.c
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@ -1,17 +0,0 @@
/* PR target/pr70799 */
/* { dg-do compile { target ia32 } } */
/* { dg-options "-O2 -march=slm -mavx512vl -mno-stackrealign" } */
/* { dg-final { scan-assembler "psllq" } } */
/* { dg-final { scan-assembler "psraq" } } */
long long a, b;
void test1 (int c)
{
a = b << c;
}
void test2 (int c)
{
a = b >> c;
}

13
gcc/testsuite/gcc.target/i386/pr89902.c Normal file
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@ -0,0 +1,13 @@
/* PR target/89902 */
/* { dg-do compile { target ia32 } } */
/* { dg-options "-O2 -fno-tree-coalesce-vars -mavx512bitalg" } */
void bar (void);
int
foo (long long x)
{
x <<= (char) x;
bar ();
return x;
}

14
gcc/testsuite/gcc.target/i386/pr89903.c Normal file
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@ -0,0 +1,14 @@
/* PR target/89903 */
/* { dg-do compile { target ia32 } } */
/* { dg-options "-O2 -march=skylake" } */
int a, b;
void
foo (void)
{
unsigned long long d = 983040;
d += a;
d >>= (short) d;
b = d;
}