config.gcc: Revamp target_cpu_default2 to strings; support new x86 variants.
* config.gcc: Revamp target_cpu_default2 to strings; support new x86 variants. * i386.c (override_options): Default x86_cpu_string and x86_arch_string properly; set prefetch_sse. * i386.h (x86_prefetch_sse): Declare. (TARGET_PREFETCH_SSE): New. (CPP_CPU_DEFAULT_SPEC): Define according to the new macros. (TARGET_CPU_DEFAULT_*): New. * config/i386/i386.h (struct processor_costs): Add new members prefetch_block and simultaneous_prefetches. (PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): New. * config/i386/i386.c (processor_costs structs): Add values for prefetch_block and simultaneous_prefetches. * config/i386/i386.md (unspec values): Remove values for prefetch operations, which now use the PREFETCH rtx code. (prefetch_sse, prefetch_3dnow, prefetchw): Combine to use new unified prefetch support. From-SVN: r48006
This commit is contained in:
Jan Hubicka
parent
4ff8507ec5
commit
f436562730
@ -1,3 +1,27 @@
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Fri Dec 14 21:23:54 CET 2001 Jan Hubicka <jh@suse.cz>
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* config.gcc: Revamp target_cpu_default2 to strings;
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support new x86 variants.
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* i386.c (override_options): Default x86_cpu_string and x86_arch_string
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properly; set prefetch_sse.
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* i386.h (x86_prefetch_sse): Declare.
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(TARGET_PREFETCH_SSE): New.
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(CPP_CPU_DEFAULT_SPEC): Define according to the new macros.
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(TARGET_CPU_DEFAULT_*): New.
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Thu Dec 13 21:57:13 CET 2001 Janis Johnson <janis187@us.ibm.com>
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Jan Hubicka <jh@suse.cz>
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* config/i386/i386.h (struct processor_costs): Add new members
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prefetch_block and simultaneous_prefetches.
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(PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): New.
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* config/i386/i386.c (processor_costs structs): Add values for
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prefetch_block and simultaneous_prefetches.
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* config/i386/i386.md (unspec values): Remove values for prefetch
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operations, which now use the PREFETCH rtx code.
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(prefetch_sse, prefetch_3dnow, prefetchw): Combine to use new
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unified prefetch support.
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2001-12-14 Jason Merrill <jason@redhat.com>
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* diagnostic.c (sorry): Increment sorrycount before saving the
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@ -81,6 +81,8 @@ struct processor_costs size_cost = { /* costs for tunning for size */
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{3, 3, 3}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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};
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/* Processor costs (relative to an add) */
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static const
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@ -116,6 +118,8 @@ struct processor_costs i386_cost = { /* 386 specific costs */
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{4, 8, 16}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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};
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static const
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@ -150,7 +154,9 @@ struct processor_costs i486_cost = { /* 486 specific costs */
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in SImode, DImode and TImode */
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{4, 8, 16}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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3 /* MMX or SSE register to integer */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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};
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static const
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@ -185,7 +191,9 @@ struct processor_costs pentium_cost = {
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in SImode, DImode and TImode */
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{4, 8, 16}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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3 /* MMX or SSE register to integer */
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3, /* MMX or SSE register to integer */
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0, /* size of prefetch block */
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0, /* number of parallel prefetches */
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};
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static const
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@ -220,7 +228,9 @@ struct processor_costs pentiumpro_cost = {
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in SImode, DImode and TImode */
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{2, 2, 8}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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3 /* MMX or SSE register to integer */
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3, /* MMX or SSE register to integer */
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32, /* size of prefetch block */
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6, /* number of parallel prefetches */
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};
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static const
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@ -255,7 +265,9 @@ struct processor_costs k6_cost = {
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in SImode, DImode and TImode */
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{2, 2, 8}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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6 /* MMX or SSE register to integer */
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6, /* MMX or SSE register to integer */
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32, /* size of prefetch block */
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1, /* number of parallel prefetches */
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};
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static const
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@ -290,7 +302,9 @@ struct processor_costs athlon_cost = {
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in SImode, DImode and TImode */
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{2, 2, 8}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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6 /* MMX or SSE register to integer */
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6, /* MMX or SSE register to integer */
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64, /* size of prefetch block */
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6, /* number of parallel prefetches */
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};
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static const
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@ -326,6 +340,8 @@ struct processor_costs pentium4_cost = {
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{2, 2, 8}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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10, /* MMX or SSE register to integer */
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64, /* size of prefetch block */
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6, /* number of parallel prefetches */
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};
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const struct processor_costs *ix86_cost = &pentium_cost;
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@ -592,6 +608,9 @@ const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
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/* # of registers to use to pass arguments. */
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const char *ix86_regparm_string;
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/* true if sse prefetch instruction is not NOOP. */
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int x86_prefetch_sse;
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/* ix86_regparm_string as a number */
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int ix86_regparm;
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@ -817,6 +836,7 @@ override_options ()
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{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0, 1}
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};
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static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
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static struct pta
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{
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const char *const name; /* processor name or nickname. */
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@ -826,7 +846,7 @@ override_options ()
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PTA_SSE = 1,
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PTA_SSE2 = 2,
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PTA_MMX = 4,
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PTA_SSEPREFETCH = 8,
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PTA_PREFETCH_SSE = 8,
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PTA_3DNOW = 16,
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PTA_3DNOW_A = 64
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} flags;
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@ -841,21 +861,21 @@ override_options ()
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{"i686", PROCESSOR_PENTIUMPRO, 0},
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{"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
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{"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
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{"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSEPREFETCH},
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{"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
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{"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 |
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PTA_MMX | PTA_SSEPREFETCH},
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PTA_MMX | PTA_PREFETCH_SSE},
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{"k6", PROCESSOR_K6, PTA_MMX},
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{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
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{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
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{"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
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{"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
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| PTA_3DNOW_A},
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{"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH
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{"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
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| PTA_3DNOW | PTA_3DNOW_A},
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{"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
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{"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
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| PTA_3DNOW_A | PTA_SSE},
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{"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
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{"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
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| PTA_3DNOW_A | PTA_SSE},
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{"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_SSEPREFETCH | PTA_3DNOW
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{"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
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| PTA_3DNOW_A | PTA_SSE},
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};
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@ -865,8 +885,12 @@ override_options ()
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SUBTARGET_OVERRIDE_OPTIONS;
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#endif
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ix86_arch = PROCESSOR_I386;
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ix86_cpu = (enum processor_type) TARGET_CPU_DEFAULT;
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if (!ix86_cpu_string && ix86_arch_string)
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ix86_cpu_string = ix86_arch_string;
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if (!ix86_cpu_string)
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ix86_cpu_string = cpu_names [TARGET_CPU_DEFAULT];
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if (!ix86_arch_string)
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ix86_arch_string = TARGET_64BIT ? "athlon-4" : "i386";
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if (ix86_cmodel_string != 0)
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{
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@ -900,47 +924,45 @@ override_options ()
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sorry ("%i-bit mode not compiled in",
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(target_flags & MASK_64BIT) ? 64 : 32);
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if (ix86_arch_string != 0)
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{
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for (i = 0; i < pta_size; i++)
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if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
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{
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ix86_arch = processor_alias_table[i].processor;
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/* Default cpu tuning to the architecture. */
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ix86_cpu = ix86_arch;
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if (processor_alias_table[i].flags & PTA_MMX
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&& !(target_flags & MASK_MMX_SET))
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target_flags |= MASK_MMX;
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if (processor_alias_table[i].flags & PTA_3DNOW
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&& !(target_flags & MASK_3DNOW_SET))
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target_flags |= MASK_3DNOW;
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if (processor_alias_table[i].flags & PTA_3DNOW_A
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&& !(target_flags & MASK_3DNOW_A_SET))
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target_flags |= MASK_3DNOW_A;
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if (processor_alias_table[i].flags & PTA_SSE
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&& !(target_flags & MASK_SSE_SET))
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target_flags |= MASK_SSE;
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if (processor_alias_table[i].flags & PTA_SSE2
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&& !(target_flags & MASK_SSE2_SET))
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target_flags |= MASK_SSE2;
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break;
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}
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for (i = 0; i < pta_size; i++)
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if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
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{
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ix86_arch = processor_alias_table[i].processor;
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/* Default cpu tuning to the architecture. */
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ix86_cpu = ix86_arch;
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if (processor_alias_table[i].flags & PTA_MMX
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&& !(target_flags & MASK_MMX_SET))
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target_flags |= MASK_MMX;
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if (processor_alias_table[i].flags & PTA_3DNOW
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&& !(target_flags & MASK_3DNOW_SET))
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target_flags |= MASK_3DNOW;
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if (processor_alias_table[i].flags & PTA_3DNOW_A
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&& !(target_flags & MASK_3DNOW_A_SET))
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target_flags |= MASK_3DNOW_A;
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if (processor_alias_table[i].flags & PTA_SSE
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&& !(target_flags & MASK_SSE_SET))
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target_flags |= MASK_SSE;
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if (processor_alias_table[i].flags & PTA_SSE2
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&& !(target_flags & MASK_SSE2_SET))
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target_flags |= MASK_SSE2;
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if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
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x86_prefetch_sse = true;
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break;
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}
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if (i == pta_size)
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error ("bad value (%s) for -march= switch", ix86_arch_string);
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}
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if (i == pta_size)
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error ("bad value (%s) for -march= switch", ix86_arch_string);
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if (ix86_cpu_string != 0)
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{
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for (i = 0; i < pta_size; i++)
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if (! strcmp (ix86_cpu_string, processor_alias_table[i].name))
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{
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ix86_cpu = processor_alias_table[i].processor;
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break;
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}
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if (i == pta_size)
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error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
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}
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for (i = 0; i < pta_size; i++)
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if (! strcmp (ix86_cpu_string, processor_alias_table[i].name))
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{
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ix86_cpu = processor_alias_table[i].processor;
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break;
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}
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if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
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x86_prefetch_sse = true;
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if (i == pta_size)
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error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
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if (optimize_size)
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ix86_cost = &size_cost;
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@ -11857,22 +11879,13 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
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return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3, arglist, target);
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case IX86_BUILTIN_PREFETCH_3DNOW:
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case IX86_BUILTIN_PREFETCHW:
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icode = CODE_FOR_prefetch_3dnow;
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arg0 = TREE_VALUE (arglist);
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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op1 = (fcode == IX86_BUILTIN_PREFETCH_3DNOW ? const0_rtx : const1_rtx);
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mode0 = insn_data[icode].operand[0].mode;
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pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
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if (! pat)
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return NULL_RTX;
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emit_insn (pat);
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return NULL_RTX;
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case IX86_BUILTIN_PREFETCHW:
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icode = CODE_FOR_prefetchw;
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arg0 = TREE_VALUE (arglist);
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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mode0 = insn_data[icode].operand[0].mode;
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pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
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pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0), op1);
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if (! pat)
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return NULL_RTX;
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emit_insn (pat);
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@ -86,6 +86,9 @@ struct processor_costs {
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in SImode, DImode and TImode*/
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const int mmxsse_to_integer; /* cost of moving mmxsse register to
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integer and vice versa. */
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const int prefetch_block; /* bytes moved to cache for prefetch. */
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const int simultaneous_prefetches; /* number of parallel prefetch
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operations. */
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};
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extern const struct processor_costs *ix86_cost;
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@ -224,6 +227,7 @@ extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
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extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
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extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
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extern const int x86_epilogue_using_move, x86_decompose_lea;
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extern int x86_prefetch_sse;
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#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
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#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
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@ -262,6 +266,7 @@ extern const int x86_epilogue_using_move, x86_decompose_lea;
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#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
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#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
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#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
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#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
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#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
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@ -480,24 +485,61 @@ extern int ix86_arch;
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%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
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#endif
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#define TARGET_CPU_DEFAULT_i386 0
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#define TARGET_CPU_DEFAULT_i486 1
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#define TARGET_CPU_DEFAULT_pentium 2
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#define TARGET_CPU_DEFAULT_pentiumpro 3
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#define TARGET_CPU_DEFAULT_pentium2 4
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#define TARGET_CPU_DEFAULT_pentium3 5
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#define TARGET_CPU_DEFAULT_pentium4 6
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#define TARGET_CPU_DEFAULT_k6 7
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#define TARGET_CPU_DEFAULT_k6_2 8
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#define TARGET_CPU_DEFAULT_k6_3 9
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#define TARGET_CPU_DEFAULT_athlon 10
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#define TARGET_CPU_DEFAULT_athlon_sse 11
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#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
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"pentiumpro", "pentium2", "pentium3", \
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"pentium4", "k6", "k6-2", "k6-3",\
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"athlon", "athlon-4"}
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#ifndef CPP_CPU_DEFAULT_SPEC
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#if TARGET_CPU_DEFAULT == 1
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#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
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#endif
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#if TARGET_CPU_DEFAULT == 2
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#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
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#endif
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#if TARGET_CPU_DEFAULT == 3
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#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
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#endif
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#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
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#endif
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#if TARGET_CPU_DEFAULT == 4
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#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
|
||||
-D__tune_pentium2__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
|
||||
-D__tune_pentium2__ -D__tune_pentium3__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == 5
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
|
||||
#endif
|
||||
#if TARGET_CPU_DEFAULT == 6
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
|
||||
#endif
|
||||
#ifndef CPP_CPU_DEFAULT_SPEC
|
||||
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
|
||||
@ -531,30 +573,45 @@ extern int ix86_arch;
|
||||
%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
|
||||
%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
|
||||
%{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
|
||||
%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
|
||||
-D__pentium__mmx__ \
|
||||
%{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
|
||||
%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
|
||||
-D__pentiumpro -D__pentiumpro__ \
|
||||
%{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
|
||||
%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
|
||||
%{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
|
||||
%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
|
||||
%{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
|
||||
%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
|
||||
%{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
|
||||
%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
|
||||
%{!mcpu*:-D__tune_athlon__ }}\
|
||||
%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
|
||||
-D__athlon_sse__ \
|
||||
%{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
|
||||
%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
|
||||
%{m386|mcpu=i386:-D__tune_i386__ }\
|
||||
%{m486|mcpu=i486:-D__tune_i486__ }\
|
||||
%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
|
||||
%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__\
|
||||
%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
|
||||
-D__tune_pentiumpro__ }\
|
||||
%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
|
||||
%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
|
||||
-D__tune_athlon__ }\
|
||||
%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
|
||||
-D__tune_athlon_sse__ }\
|
||||
%{mcpu=pentium4:-D__tune_pentium4__ }\
|
||||
%{march=march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
|
||||
-D__SSE__ }\
|
||||
%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
|
||||
march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
|
||||
|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
|
||||
%{march=k6|march=k6-2|march=k6-3\
|
||||
%{march=k6-2|march=k6-3\
|
||||
march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
|
||||
|march=athlon-mp: -D__3dNOW__ }\
|
||||
%{mcpu=mcpu=pentium4: -D__SSE2__ }\
|
||||
%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
|
||||
|march=athlon-mp: -D__3dNOW_A__ }\
|
||||
%{march=mcpu=pentium4: -D__SSE2__ }\
|
||||
%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
|
||||
|
||||
#ifndef CPP_CPU_SPEC
|
||||
@ -2261,6 +2318,12 @@ while (0)
|
||||
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
||||
#define DEFAULT_SIGNED_CHAR 1
|
||||
|
||||
/* Number of bytes moved into a data cache for a single prefetch operation. */
|
||||
#define PREFETCH_BLOCK ix86_cost->prefetch_block
|
||||
|
||||
/* Number of prefetch operations that can be done in parallel. */
|
||||
#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
|
||||
|
||||
/* Max number of bytes we can move from memory to memory
|
||||
in one reasonably fast instruction. */
|
||||
#define MOVE_MAX 16
|
||||
|
||||
@ -93,8 +93,6 @@
|
||||
;; 44 This is a `sfence' operation.
|
||||
;; 45 This is a noop to prevent excessive combiner cleverness.
|
||||
;; 46 This is a `femms' operation.
|
||||
;; 47 This is a `prefetch' (3DNow) operation.
|
||||
;; 48 This is a `prefetchw' operation.
|
||||
;; 49 This is a 'pavgusb' operation.
|
||||
;; 50 This is a `pfrcp' operation.
|
||||
;; 51 This is a `pfrcpit1' operation.
|
||||
@ -19400,10 +19398,58 @@
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "memory" "unknown")])
|
||||
|
||||
(define_expand "prefetch"
|
||||
[(prefetch (match_operand:SI 0 "address_operand" "p")
|
||||
(match_operand:SI 1 "const_int_operand" "n")
|
||||
(match_operand:SI 2 "const_int_operand" "n"))]
|
||||
"TARGET_PREFETCH_SSE || TARGET_3DNOW"
|
||||
"
|
||||
{
|
||||
int rw = INTVAL (operands[1]);
|
||||
int locality = INTVAL (operands[2]);
|
||||
if (rw != 0 && rw != 1)
|
||||
abort ();
|
||||
if (locality < 0 || locality > 3)
|
||||
abort ();
|
||||
/* Use 3dNOW prefetch in case we are asking for write prefetch not
|
||||
suported by SSE counterpart or the SSE prefetch is not available
|
||||
(K6 machines). Otherwise use SSE prefetch as it allows specifying
|
||||
of locality. */
|
||||
if (TARGET_3DNOW
|
||||
&& (!TARGET_PREFETCH_SSE || rw))
|
||||
{
|
||||
emit_insn (gen_prefetch_3dnow (operands[0], operands[1]));
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
switch (locality)
|
||||
{
|
||||
case 0: /* No temporal locality. */
|
||||
i = 0;
|
||||
break;
|
||||
case 1: /* Lowest level of temporal locality. */
|
||||
i = 3;
|
||||
break;
|
||||
case 2: /* Moderate level of temporal locality. */
|
||||
i = 2;
|
||||
break;
|
||||
case 3: /* Highest level of temporal locality. */
|
||||
i = 1;
|
||||
break;
|
||||
default:
|
||||
abort (); /* We already checked for valid values above. */
|
||||
break;
|
||||
}
|
||||
emit_insn (gen_prefetch_sse (operands[0], GEN_INT (i)));
|
||||
}
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_insn "prefetch_sse"
|
||||
[(unspec [(match_operand:SI 0 "address_operand" "p")
|
||||
(match_operand:SI 1 "immediate_operand" "n")] 35)]
|
||||
"TARGET_SSE || TARGET_3DNOW_A"
|
||||
"TARGET_PREFETCH_SSE"
|
||||
{
|
||||
switch (INTVAL (operands[1]))
|
||||
{
|
||||
@ -19579,15 +19625,16 @@
|
||||
[(set_attr "type" "mmx")])
|
||||
|
||||
(define_insn "prefetch_3dnow"
|
||||
[(unspec [(match_operand:SI 0 "address_operand" "p")] 47)]
|
||||
[(prefetch (match_operand:SI 0 "address_operand" "p")
|
||||
(match_operand:SI 1 "const_int_operand" "n")
|
||||
(const_int 0))]
|
||||
"TARGET_3DNOW"
|
||||
"prefetch\\t%a0"
|
||||
[(set_attr "type" "mmx")])
|
||||
|
||||
(define_insn "prefetchw"
|
||||
[(unspec [(match_operand:SI 0 "address_operand" "p")] 48)]
|
||||
"TARGET_3DNOW"
|
||||
"prefetchw\\t%a0"
|
||||
{
|
||||
if (INTVAL (operands[1]) == 0)
|
||||
return "prefetch\t%a0";
|
||||
else
|
||||
return "prefetchw\t%a0";
|
||||
}
|
||||
[(set_attr "type" "mmx")])
|
||||
|
||||
(define_insn "pf2id"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user