testsuite/97299 - more gcc.dg/vect/slp-reduc-3.c massaging
This adds more guards to the VEC_PERM_EXPR scan, namely that we also could end up with load-lanes and of course no vectorization at all. Need dependent scans (scan-if-scan-X PASSed ...). 2021-01-21 Richard Biener <rguenther@suse.de> PR testsuite/97299 * gcc.dg/vect/slp-reduc-3.c: Amend target selectors.
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@ -46,6 +46,7 @@ int main (void)
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for (i=0; i<N; i++) {
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for (i=0; i<N; i++) {
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X[i] = i;
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X[i] = i;
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Y[i] = 64-i;
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Y[i] = 64-i;
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asm volatile ("" ::: "memory");
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}
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}
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foo1 (N/2, &dot1, &dot2);
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foo1 (N/2, &dot1, &dot2);
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@ -58,7 +59,7 @@ int main (void)
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/* The initialization loop in main also gets vectorized. */
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/* The initialization loop in main also gets vectorized. */
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/* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */
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/* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } */
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } } } } */
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/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } } } */
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/* Check we can elide permutes if SLP vectorizing the reduction. */
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/* Check we can elide permutes if SLP vectorizing the reduction. */
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/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } } } } */
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/* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { { { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } && { ! vect_load_lanes } } && { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } } */
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