driver-i386.c (describe_cache): Add l2_sizekb argument.
* config/i386/driver-i386.c (describe_cache): Add l2_sizekb argument. Pass L2 size as "--param l2-cache-size" to the compiler. (decode_l2_cache): New function to decode L2 cache parameters using 0x8000006 extended cpuid function. (detect_caches_amd): Determine parameters of L2 cache using decode_l2_caches function. (decode_caches_intel): Decode L2 cache parameters. (detect_caches_intel): Determine L2 cache parameters using decode_caches_intel and decode_l2_caches functions. From-SVN: r133890
This commit is contained in:
Zuxy Meng
Uros Bizjak
parent
3ee909cb67
commit
f4a1dd0dc7
@ -1,3 +1,15 @@
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2008-04-04 Zuxy Meng <zuxy.meng@gmail.com>
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* config/i386/driver-i386.c (describe_cache): Add l2_sizekb argument.
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Pass L2 size as "--param l2-cache-size" to the compiler.
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(decode_l2_cache): New function to decode L2 cache parameters using
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0x8000006 extended cpuid function.
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(detect_caches_amd): Determine parameters of L2 cache using
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decode_l2_caches function.
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(decode_caches_intel): Decode L2 cache parameters.
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(detect_caches_intel): Determine L2 cache parameters using
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decode_caches_intel and decode_l2_caches functions.
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2008-04-03 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa/xtensa.c (xtensa_secondary_reload_class): Use a
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@ -33,17 +33,39 @@ const char *host_detect_local_cpu (int argc, const char **argv);
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static char *
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describe_cache (unsigned l1_sizekb, unsigned l1_line,
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unsigned l1_assoc ATTRIBUTE_UNUSED)
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unsigned l1_assoc ATTRIBUTE_UNUSED, unsigned l2_sizekb)
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{
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char size[100], line[100];
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char size[100], line[100], size2[100];
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/* At the moment, gcc middle-end does not use the information about the
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associativity of the cache. */
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sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
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sprintf (line, "--param l1-cache-line-size=%u", l1_line);
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sprintf (size2, "--param l2-cache-size=%u", l2_sizekb);
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return concat (size, " ", line, " ", NULL);
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return concat (size, " ", line, " ", size2, " ", NULL);
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}
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static void
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decode_l2_cache (unsigned *l2_size, unsigned *l2_line, unsigned *l2_assoc)
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{
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unsigned eax, ebx, ecx, edx, assoc;
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__cpuid (0x80000006, eax, ebx, ecx, edx);
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*l2_size = (ecx >> 16) & 0xffff;
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*l2_line = ecx & 0xff;
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assoc = (ecx >> 12) & 0xf;
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if (assoc == 6)
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assoc = 8;
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else if (assoc == 8)
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assoc = 16;
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else if (assoc >= 0xa && assoc <= 0xc)
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assoc = 32 + (assoc - 0xa) * 16;
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else if (assoc >= 0xd && assoc <= 0xe)
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assoc = 96 + (assoc - 0xd) * 32;
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*l2_assoc = assoc;
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}
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/* Returns the description of caches for an AMD processor. */
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@ -53,6 +75,7 @@ detect_caches_amd (unsigned max_ext_level)
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{
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unsigned eax, ebx, ecx, edx;
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unsigned l1_sizekb, l1_line, l1_assoc;
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unsigned l2_sizekb, l2_line, l2_assoc;
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if (max_ext_level < 0x80000005)
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return (char *) "";
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@ -63,15 +86,20 @@ detect_caches_amd (unsigned max_ext_level)
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l1_sizekb = (ecx >> 24) & 0xff;
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l1_assoc = (ecx >> 16) & 0xff;
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return describe_cache (l1_sizekb, l1_line, l1_assoc);
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if (max_ext_level >= 0x80000006)
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decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
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return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
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}
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/* Stores the size of the L1 cache and cache line, and the associativity
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of the cache according to REG to L1_SIZEKB, L1_LINE and L1_ASSOC. */
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/* Stores the size of the L1/2 cache and cache line, and the associativity
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of the cache according to REG to L1_SIZEKB, L1_LINE, L1_ASSOC and
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L2_SIZEKB. */
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static void
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decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
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unsigned *l1_assoc)
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unsigned *l1_assoc, unsigned *l2_sizekb,
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unsigned *l2_line, unsigned *l2_assoc)
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{
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unsigned i, val;
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@ -100,6 +128,66 @@ decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
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*l1_line = 64;
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*l1_assoc = 8;
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break;
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case 0x39:
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*l2_sizekb = 128;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x3a:
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*l2_sizekb = 192;
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*l2_line = 64;
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*l2_assoc = 6;
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break;
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case 0x3b:
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*l2_sizekb = 128;
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*l2_line = 64;
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*l2_assoc = 2;
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break;
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case 0x3c:
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*l2_sizekb = 256;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x3d:
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*l2_sizekb = 384;
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*l2_line = 64;
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*l2_assoc = 6;
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break;
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case 0x3e:
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*l2_sizekb = 512;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x41:
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*l2_sizekb = 128;
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*l2_line = 32;
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*l2_assoc = 4;
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break;
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case 0x42:
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*l2_sizekb = 256;
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*l2_line = 32;
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*l2_assoc = 4;
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break;
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case 0x43:
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*l2_sizekb = 512;
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*l2_line = 32;
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*l2_assoc = 4;
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break;
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case 0x44:
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*l2_sizekb = 1024;
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*l2_line = 32;
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*l2_assoc = 4;
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break;
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case 0x45:
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*l2_sizekb = 2048;
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*l2_line = 32;
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*l2_assoc = 4;
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break;
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case 0x49:
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*l2_sizekb = 4096;
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*l2_line = 64;
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*l2_assoc = 16;
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break;
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case 0x60:
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*l1_sizekb = 16;
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*l1_line = 64;
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@ -120,6 +208,71 @@ decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
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*l1_line = 64;
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*l1_assoc = 4;
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break;
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case 0x78:
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*l2_sizekb = 1024;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x79:
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*l2_sizekb = 128;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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case 0x7a:
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*l2_sizekb = 256;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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case 0x7b:
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*l2_sizekb = 512;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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case 0x7c:
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*l2_sizekb = 1024;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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case 0x7d:
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*l2_sizekb = 2048;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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case 0x7f:
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*l2_sizekb = 512;
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*l2_line = 64;
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*l2_assoc = 2;
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break;
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case 0x82:
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*l2_sizekb = 256;
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*l2_line = 32;
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*l2_assoc = 8;
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break;
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case 0x83:
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*l2_sizekb = 512;
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*l2_line = 32;
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*l2_assoc = 8;
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break;
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case 0x84:
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*l2_sizekb = 1024;
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*l2_line = 32;
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*l2_assoc = 8;
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break;
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case 0x85:
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*l2_sizekb = 2048;
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*l2_line = 32;
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*l2_assoc = 8;
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break;
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case 0x86:
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*l2_sizekb = 512;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x87:
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*l2_sizekb = 1024;
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*l2_line = 64;
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*l2_assoc = 8;
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break;
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default:
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break;
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@ -130,25 +283,34 @@ decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
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/* Returns the description of caches for an intel processor. */
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static char *
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detect_caches_intel (unsigned max_level)
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detect_caches_intel (unsigned max_level, unsigned max_ext_level)
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{
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unsigned eax, ebx, ecx, edx;
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unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
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unsigned l2_sizekb = 0, l2_line = 0, l2_assoc = 0;
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if (max_level < 2)
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return (char *) "";
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__cpuid (2, eax, ebx, ecx, edx);
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decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc);
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decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc);
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decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc);
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decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc);
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decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc,
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&l2_sizekb, &l2_line, &l2_assoc);
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decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc,
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&l2_sizekb, &l2_line, &l2_assoc);
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decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc,
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&l2_sizekb, &l2_line, &l2_assoc);
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decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc,
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&l2_sizekb, &l2_line, &l2_assoc);
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if (!l1_sizekb)
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return (char *) "";
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return describe_cache (l1_sizekb, l1_line, assoc);
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/* Newer Intel CPUs are equipped with AMD style L2 cache info */
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if (max_ext_level >= 0x80000006)
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decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
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return describe_cache (l1_sizekb, l1_line, assoc, l2_sizekb);
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}
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/* This will be called by the spec parser in gcc.c when it sees
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@ -234,7 +396,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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if (vendor == *(unsigned int*) "Auth")
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cache = detect_caches_amd (ext_level);
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else if (vendor == *(unsigned int*) "Genu")
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cache = detect_caches_intel (max_level);
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cache = detect_caches_intel (max_level, ext_level);
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}
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if (vendor == *(unsigned int*) "Auth")
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