Add pixel compare VIS intrinsics.
* config/sparc/sparc.md (UNSPEC_FCMPLE, UNSPEC_FCMPNE, UNSPEC_FCMPGT, UNSPEC_FCMPEQ): New unspec codes. (fcmple16_vis, fcmple32_vis, fcmpne16_vis, fcmpne32_vis, fcmpgt16_vis, fcmpgt32_vis, fcmpeq16_vis, fcmpeq32_vis): New patterns. * config/sparc/sparc.c (sparc_vis_init_builtins): Create builtins for new pixel compare VIS patterns. * config/sparc/visintrin.h (__vis_fcmple16, __vis_fcmple32, __vis_fcmpne16, __vis_fcmpne32, __vis_fcmpgt16, __vis_fcmpgt32, __vis_fcmpeq16, __vis_fcmpeq32): New. * doc/extend.texi: Document new pixel compare VIS intrinsics. From-SVN: r179072
This commit is contained in:
David S. Miller
David S. Miller
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bc35416dfc
commit
f4d7f82866
@ -76,6 +76,17 @@
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(sparc_vis_init_builtins): Use def_builtin_const for all VIS builtins
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other than alignaddr and falignaddr.
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* config/sparc/sparc.md (UNSPEC_FCMPLE, UNSPEC_FCMPNE, UNSPEC_FCMPGT,
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UNSPEC_FCMPEQ): New unspec codes.
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(fcmple16_vis, fcmple32_vis, fcmpne16_vis, fcmpne32_vis, fcmpgt16_vis,
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fcmpgt32_vis, fcmpeq16_vis, fcmpeq32_vis): New patterns.
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* config/sparc/sparc.c (sparc_vis_init_builtins): Create builtins for
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new pixel compare VIS patterns.
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* config/sparc/visintrin.h (__vis_fcmple16, __vis_fcmple32,
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__vis_fcmpne16, __vis_fcmpne32, __vis_fcmpgt16, __vis_fcmpgt32,
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__vis_fcmpeq16, __vis_fcmpeq32): New.
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* doc/extend.texi: Document new pixel compare VIS intrinsics.
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2011-09-21 Tom de Vries <tom@codesourcery.com>
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* final.c (final): Handle if JUMP_LABEL is not LABEL_P.
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@ -9164,6 +9164,10 @@ sparc_vis_init_builtins (void)
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tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
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ptr_type_node,
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ptr_type_node, 0);
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tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
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v4hi, v4hi, 0);
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tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
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v2si, v2si, 0);
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/* Packing and expanding vectors. */
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def_builtin_const ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
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@ -9252,6 +9256,23 @@ sparc_vis_init_builtins (void)
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def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
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si_ftype_ptr_ptr);
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}
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def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16_vis,
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si_ftype_v4hi_v4hi);
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def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32_vis,
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si_ftype_v2si_v2si);
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def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16_vis,
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si_ftype_v4hi_v4hi);
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def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32_vis,
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si_ftype_v2si_v2si);
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def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16_vis,
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si_ftype_v4hi_v4hi);
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def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32_vis,
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si_ftype_v2si_v2si);
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def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16_vis,
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si_ftype_v4hi_v4hi);
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def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32_vis,
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si_ftype_v2si_v2si);
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}
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/* Handle TARGET_EXPAND_BUILTIN target hook.
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@ -70,6 +70,11 @@
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(UNSPEC_SP_SET 60)
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(UNSPEC_SP_TEST 61)
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(UNSPEC_FCMPLE 70)
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(UNSPEC_FCMPNE 71)
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(UNSPEC_FCMPGT 72)
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(UNSPEC_FCMPEQ 73)
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])
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(define_constants
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@ -7886,4 +7891,84 @@
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"edge32l\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "fcmple16_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
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(match_operand:V4HI 2 "register_operand" "e")]
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UNSPEC_FCMPLE))]
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"TARGET_VIS"
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"fcmple16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmple32_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V2SI 2 "register_operand" "e")]
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UNSPEC_FCMPLE))]
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"TARGET_VIS"
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"fcmple32\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpne16_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
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(match_operand:V4HI 2 "register_operand" "e")]
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UNSPEC_FCMPNE))]
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"TARGET_VIS"
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"fcmpne16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpne32_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V2SI 2 "register_operand" "e")]
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UNSPEC_FCMPNE))]
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"TARGET_VIS"
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"fcmpne32\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpgt16_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
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(match_operand:V4HI 2 "register_operand" "e")]
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UNSPEC_FCMPGT))]
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"TARGET_VIS"
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"fcmpgt16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpgt32_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V2SI 2 "register_operand" "e")]
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UNSPEC_FCMPGT))]
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"TARGET_VIS"
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"fcmpgt32\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpeq16_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
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(match_operand:V4HI 2 "register_operand" "e")]
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UNSPEC_FCMPEQ))]
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"TARGET_VIS"
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"fcmpeq16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fcmpeq32_vis"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V2SI 2 "register_operand" "e")]
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UNSPEC_FCMPEQ))]
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"TARGET_VIS"
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"fcmpeq32\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(include "sync.md")
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@ -206,4 +206,60 @@ __vis_edge32l (void *__A, void *__B)
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return __builtin_vis_edge32l (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmple16 (__v4hi __A, __v4hi __B)
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{
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return __builtin_vis_fcmple16 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmple32 (__v2si __A, __v2si __B)
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{
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return __builtin_vis_fcmple32 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpne16 (__v4hi __A, __v4hi __B)
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{
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return __builtin_vis_fcmpne16 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpne32 (__v2si __A, __v2si __B)
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{
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return __builtin_vis_fcmpne32 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpgt16 (__v4hi __A, __v4hi __B)
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{
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return __builtin_vis_fcmpgt16 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpgt32 (__v2si __A, __v2si __B)
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{
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return __builtin_vis_fcmpgt32 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpeq16 (__v4hi __A, __v4hi __B)
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{
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return __builtin_vis_fcmpeq16 (__A, __B);
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}
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_fcmpeq32 (__v2si __A, __v2si __B)
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{
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return __builtin_vis_fcmpeq32 (__A, __B);
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}
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#endif /* _VISINTRIN_H_INCLUDED */
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@ -12965,6 +12965,15 @@ int __builtin_vis_edge16 (void *, void *);
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int __builtin_vis_edge16l (void *, void *);
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int __builtin_vis_edge32 (void *, void *);
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int __builtin_vis_edge32l (void *, void *);
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int __builtin_vis_fcmple16 (v4hi, v4hi);
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int __builtin_vis_fcmple32 (v2si, v2si);
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int __builtin_vis_fcmpne16 (v4hi, v4hi);
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int __builtin_vis_fcmpne32 (v2si, v2si);
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int __builtin_vis_fcmpgt16 (v4hi, v4hi);
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int __builtin_vis_fcmpgt32 (v2si, v2si);
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int __builtin_vis_fcmpeq16 (v4hi, v4hi);
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int __builtin_vis_fcmpeq32 (v2si, v2si);
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@end smallexample
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@node SPU Built-in Functions
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