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ira.h (target_ira): Delete x_ira_available_class_regs.

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gcc/
	* ira.h (target_ira): Delete x_ira_available_class_regs.
	(ira_available_class_regs): Delete.
	* ira.c (setup_available_class_regs): Delete.
	(setup_alloc_classes): Don't call it.
	(setup_pressure_classes): Use ira_class_hard_regs_num instead of
	ira_available_class_regs.
	* haifa-sched.c (print_curr_reg_pressure, setup_insn_reg_pressure_info)
	(model_spill_cost): Likewise.
	* ira-build.c (low_pressure_loop_node_p): Likewise.
	* ira-color.c (color_pass): Likewise.
	* ira-emit.c (change_loop): Likewise.
	* ira-lives.c (inc_register_pressure, dec_register_pressure)
	(single_reg_class, ira_implicitly_set_insn_hard_regs)
	(process_bb_node_lives): Likewise.
	* loop-invariant.c (gain_for_invariant): Likewise.

From-SVN: r188041
This commit is contained in:
Richard Sandiford 2012-05-31 05:27:03 +00:00 committed by Richard Sandiford
parent 2e14fbda6c
commit f508f827b1
9 changed files with 40 additions and 46 deletions
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18
gcc/ChangeLog
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@ -1,3 +1,21 @@
2012-05-31 Richard Sandiford <rdsandiford@googlemail.com>
* ira.h (target_ira): Delete x_ira_available_class_regs.
(ira_available_class_regs): Delete.
* ira.c (setup_available_class_regs): Delete.
(setup_alloc_classes): Don't call it.
(setup_pressure_classes): Use ira_class_hard_regs_num instead of
ira_available_class_regs.
* haifa-sched.c (print_curr_reg_pressure, setup_insn_reg_pressure_info)
(model_spill_cost): Likewise.
* ira-build.c (low_pressure_loop_node_p): Likewise.
* ira-color.c (color_pass): Likewise.
* ira-emit.c (change_loop): Likewise.
* ira-lives.c (inc_register_pressure, dec_register_pressure)
(single_reg_class, ira_implicitly_set_insn_hard_regs)
(process_bb_node_lives): Likewise.
* loop-invariant.c (gain_for_invariant): Likewise.
2012-05-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/52999

10
gcc/haifa-sched.c
View File

@ -1085,7 +1085,7 @@ print_curr_reg_pressure (void)
gcc_assert (curr_reg_pressure[cl] >= 0);
fprintf (sched_dump, " %s:%d(%d)", reg_class_names[cl],
curr_reg_pressure[cl],
curr_reg_pressure[cl] - ira_available_class_regs[cl]);
curr_reg_pressure[cl] - ira_class_hard_regs_num[cl]);
}
fprintf (sched_dump, "\n");
}
@ -1634,9 +1634,9 @@ setup_insn_reg_pressure_info (rtx insn)
cl = ira_pressure_classes[i];
gcc_assert (curr_reg_pressure[cl] >= 0);
change = (int) pressure_info[i].set_increase - death[cl];
before = MAX (0, max_reg_pressure[i] - ira_available_class_regs[cl]);
before = MAX (0, max_reg_pressure[i] - ira_class_hard_regs_num[cl]);
after = MAX (0, max_reg_pressure[i] + change
- ira_available_class_regs[cl]);
- ira_class_hard_regs_num[cl]);
hard_regno = ira_class_hard_regs[cl][0];
gcc_assert (hard_regno >= 0);
mode = reg_raw_mode[hard_regno];
@ -2227,7 +2227,7 @@ model_recompute (rtx insn)
/* Return the cost of increasing the pressure in class CL from FROM to TO.
Here we use the very simplistic cost model that every register above
ira_available_class_regs[CL] has a spill cost of 1. We could use other
ira_class_hard_regs_num[CL] has a spill cost of 1. We could use other
measures instead, such as one based on MEMORY_MOVE_COST. However:
(1) In order for an instruction to be scheduled, the higher cost
@ -2251,7 +2251,7 @@ model_recompute (rtx insn)
static int
model_spill_cost (int cl, int from, int to)
{
from = MAX (from, ira_available_class_regs[cl]);
from = MAX (from, ira_class_hard_regs_num[cl]);
return MAX (to, from) - from;
}

4
gcc/ira-build.c
View File

@ -1829,8 +1829,8 @@ low_pressure_loop_node_p (ira_loop_tree_node_t node)
for (i = 0; i < ira_pressure_classes_num; i++)
{
pclass = ira_pressure_classes[i];
if (node->reg_pressure[pclass] > ira_available_class_regs[pclass]
&& ira_available_class_regs[pclass] > 1)
if (node->reg_pressure[pclass] > ira_class_hard_regs_num[pclass]
&& ira_class_hard_regs_num[pclass] > 1)
return false;
}
return true;

4
gcc/ira-color.c
View File

@ -2766,7 +2766,7 @@ color_pass (ira_loop_tree_node_t loop_tree_node)
pclass = ira_pressure_class_translate[rclass];
if (flag_ira_region == IRA_REGION_MIXED
&& (loop_tree_node->reg_pressure[pclass]
<= ira_available_class_regs[pclass]))
<= ira_class_hard_regs_num[pclass]))
{
mode = ALLOCNO_MODE (a);
hard_regno = ALLOCNO_HARD_REGNO (a);
@ -2819,7 +2819,7 @@ color_pass (ira_loop_tree_node_t loop_tree_node)
ALLOCNO_NUM (subloop_allocno)));
if ((flag_ira_region == IRA_REGION_MIXED)
&& (loop_tree_node->reg_pressure[pclass]
<= ira_available_class_regs[pclass]))
<= ira_class_hard_regs_num[pclass]))
{
if (! ALLOCNO_ASSIGNED_P (subloop_allocno))
{

2
gcc/ira-emit.c
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@ -606,7 +606,7 @@ change_loop (ira_loop_tree_node_t node)
== ALLOCNO_HARD_REGNO (parent_allocno))
&& (ALLOCNO_HARD_REGNO (allocno) < 0
|| (parent->reg_pressure[pclass] + 1
<= ira_available_class_regs[pclass])
<= ira_class_hard_regs_num[pclass])
|| TEST_HARD_REG_BIT (ira_prohibited_mode_move_regs
[ALLOCNO_MODE (allocno)],
ALLOCNO_HARD_REGNO (allocno))

16
gcc/ira-lives.c
View File

@ -192,7 +192,7 @@ inc_register_pressure (enum reg_class pclass, int n)
continue;
curr_reg_pressure[cl] += n;
if (high_pressure_start_point[cl] < 0
&& (curr_reg_pressure[cl] > ira_available_class_regs[cl]))
&& (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
high_pressure_start_point[cl] = curr_point;
if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
@ -221,7 +221,7 @@ dec_register_pressure (enum reg_class pclass, int nregs)
curr_reg_pressure[cl] -= nregs;
ira_assert (curr_reg_pressure[cl] >= 0);
if (high_pressure_start_point[cl] >= 0
&& curr_reg_pressure[cl] <= ira_available_class_regs[cl])
&& curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
set_p = true;
}
if (set_p)
@ -235,7 +235,7 @@ dec_register_pressure (enum reg_class pclass, int nregs)
if (! ira_reg_pressure_class_p[cl])
continue;
if (high_pressure_start_point[cl] >= 0
&& curr_reg_pressure[cl] <= ira_available_class_regs[cl])
&& curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
high_pressure_start_point[cl] = -1;
}
}
@ -851,7 +851,7 @@ single_reg_class (const char *constraints, rtx op, rtx equiv_const)
? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c, constraints));
if ((cl != NO_REGS && next_cl != cl)
|| (ira_available_class_regs[next_cl]
|| (ira_class_hard_regs_num[next_cl]
> ira_reg_class_max_nregs[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
@ -864,7 +864,7 @@ single_reg_class (const char *constraints, rtx op, rtx equiv_const)
recog_data.operand[c - '0'], NULL_RTX);
if ((cl != NO_REGS && next_cl != cl)
|| next_cl == NO_REGS
|| (ira_available_class_regs[next_cl]
|| (ira_class_hard_regs_num[next_cl]
> ira_reg_class_max_nregs[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
@ -943,8 +943,8 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
if (cl != NO_REGS
/* There is no register pressure problem if all of the
regs in this class are fixed. */
&& ira_available_class_regs[cl] != 0
&& (ira_available_class_regs[cl]
&& ira_class_hard_regs_num[cl] != 0
&& (ira_class_hard_regs_num[cl]
<= ira_reg_class_max_nregs[cl][mode]))
IOR_HARD_REG_SET (*set, reg_class_contents[cl]);
break;
@ -1170,7 +1170,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
ira_assert (curr_reg_pressure[cl]
<= ira_available_class_regs[cl]);
<= ira_class_hard_regs_num[cl]);
}
}
EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)

24
gcc/ira.c
View File

@ -490,23 +490,6 @@ setup_class_hard_regs (void)
}
}
/* Set up IRA_AVAILABLE_CLASS_REGS. */
static void
setup_available_class_regs (void)
{
int i, j;
memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs));
for (i = 0; i < N_REG_CLASSES; i++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
if (TEST_HARD_REG_BIT (temp_hard_regset, j))
ira_available_class_regs[i]++;
}
}
/* Set up global variables defining info about hard registers for the
allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
that we can use the hard frame pointer for the allocation. */
@ -520,7 +503,6 @@ setup_alloc_regs (bool use_hard_frame_p)
if (! use_hard_frame_p)
SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
setup_class_hard_regs ();
setup_available_class_regs ();
}
@ -799,9 +781,9 @@ setup_pressure_classes (void)
n = 0;
for (cl = 0; cl < N_REG_CLASSES; cl++)
{
if (ira_available_class_regs[cl] == 0)
if (ira_class_hard_regs_num[cl] == 0)
continue;
if (ira_available_class_regs[cl] != 1
if (ira_class_hard_regs_num[cl] != 1
/* A register class without subclasses may contain a few
hard registers and movement between them is costly
(e.g. SPARC FPCC registers). We still should consider it
@ -1504,7 +1486,7 @@ ira_init_register_move_cost (enum machine_mode mode)
{
/* Some subclasses are to small to have enough registers to hold
a value of MODE. Just ignore them. */
if (ira_reg_class_max_nregs[cl1][mode] > ira_available_class_regs[cl1])
if (ira_reg_class_max_nregs[cl1][mode] > ira_class_hard_regs_num[cl1])
continue;
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);

6
gcc/ira.h
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@ -25,10 +25,6 @@ along with GCC; see the file COPYING3. If not see
extern bool ira_conflicts_p;
struct target_ira {
/* Number of given class hard registers available for the register
allocation for given classes. */
int x_ira_available_class_regs[N_REG_CLASSES];
/* Map: hard register number -> allocno class it belongs to. If the
corresponding class is NO_REGS, the hard register is not available
for allocation. */
@ -95,8 +91,6 @@ extern struct target_ira *this_target_ira;
#define this_target_ira (&default_target_ira)
#endif
#define ira_available_class_regs \
(this_target_ira->x_ira_available_class_regs)
#define ira_hard_regno_allocno_class \
(this_target_ira->x_ira_hard_regno_allocno_class)
#define ira_allocno_classes_num \

2
gcc/loop-invariant.c
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@ -1210,7 +1210,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+ (int) regs_needed[pressure_class]
+ LOOP_DATA (curr_loop)->max_reg_pressure[pressure_class]
+ IRA_LOOP_RESERVED_REGS
> ira_available_class_regs[pressure_class])
> ira_class_hard_regs_num[pressure_class])
break;
}
if (i < ira_pressure_classes_num)