ia64.md (UNSPEC_SHRP): New.
* ia64.md (UNSPEC_SHRP): New. (dshift_count_operand): New. (ashrti3, ashrti3_internal, lshrti3, lshrti3_internal, shrp): New. * ia64.c (rtx_needs_barrier): Handle UNSPEC_SHRP. From-SVN: r90149
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@ -1,3 +1,10 @@
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2004-11-05 Richard Henderson <rth@redhat.com>
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* ia64.md (UNSPEC_SHRP): New.
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(dshift_count_operand): New.
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(ashrti3, ashrti3_internal, lshrti3, lshrti3_internal, shrp): New.
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* ia64.c (rtx_needs_barrier): Handle UNSPEC_SHRP.
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2004-11-05 Joseph S. Myers <joseph@codesourcery.com>
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* c-typeck.c (output_init_element): Return early if value is
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@ -4899,6 +4899,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
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break;
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case UNSPEC_FR_RECIP_APPROX:
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case UNSPEC_SHRP:
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need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
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need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
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break;
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@ -77,6 +77,7 @@
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(UNSPEC_RET_ADDR 26)
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(UNSPEC_SETF_EXP 27)
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(UNSPEC_FR_SQRT_RECIP_APPROX 28)
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(UNSPEC_SHRP 29)
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])
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(define_constants
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@ -335,6 +336,11 @@
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(and (match_code "const_int")
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(match_test "CONST_OK_FOR_J (INTVAL (op))"))))
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;; True if OP is a 7 bit immediate operand.
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(define_predicate "dshift_count_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) >= 0 && INTVAL (op) < 128")))
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;; True if OP is a 6 bit immediate operand.
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(define_predicate "shift_count_operand"
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(and (match_code "const_int")
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@ -4654,6 +4660,96 @@
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;; ::::::::::::::::::::
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;; ::
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;; :: 128 bit Integer Shifts and Rotates
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;; ::
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;; ::::::::::::::::::::
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(define_expand "ashrti3"
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[(set (match_operand:TI 0 "gr_register_operand" "")
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(ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")))]
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""
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{
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if (!dshift_count_operand (operands[2], DImode))
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FAIL;
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})
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(define_insn_and_split "*ashrti3_internal"
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[(set (match_operand:TI 0 "gr_register_operand" "=r")
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(ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
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(match_operand:DI 2 "dshift_count_operand" "n")))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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HOST_WIDE_INT shift = INTVAL (operands[2]);
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rtx lo = gen_lowpart (DImode, operands[1]);
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rtx hi = gen_highpart (DImode, operands[1]);
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rtx shiftlo = GEN_INT (shift & 63);
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if (shift & 64)
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{
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emit_insn (gen_ashrdi3 (lo, hi, shiftlo));
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emit_insn (gen_ashrdi3 (hi, hi, GEN_INT (63)));
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}
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else
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{
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emit_insn (gen_shrp (lo, hi, lo, shiftlo));
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emit_insn (gen_ashrdi3 (hi, hi, shiftlo));
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}
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DONE;
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})
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(define_expand "lshrti3"
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[(set (match_operand:TI 0 "gr_register_operand" "")
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(lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")))]
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""
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{
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if (!dshift_count_operand (operands[2], DImode))
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FAIL;
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})
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(define_insn_and_split "*lshrti3_internal"
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[(set (match_operand:TI 0 "gr_register_operand" "=r")
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(lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
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(match_operand:DI 2 "dshift_count_operand" "n")))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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HOST_WIDE_INT shift = INTVAL (operands[2]);
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rtx lo = gen_lowpart (DImode, operands[1]);
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rtx hi = gen_highpart (DImode, operands[1]);
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rtx shiftlo = GEN_INT (shift & 63);
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if (shift & 64)
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{
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emit_insn (gen_lshrdi3 (lo, hi, shiftlo));
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emit_move_insn (hi, const0_rtx);
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}
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else
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{
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emit_insn (gen_shrp (lo, hi, lo, shiftlo));
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emit_insn (gen_lshrdi3 (hi, hi, shiftlo));
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}
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DONE;
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})
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(define_insn "shrp"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
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(match_operand:DI 2 "gr_register_operand" "r")
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(match_operand:DI 3 "shift_count_operand" "M")]
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UNSPEC_SHRP))]
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""
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"shrp %0 = %1, %2, %3"
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[(set_attr "itanium_class" "ishf")])
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;; ::::::::::::::::::::
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;; ::
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;; :: 32 bit Integer Logical operations
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;; ::
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;; ::::::::::::::::::::
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