[AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half
This patch passes the number of units to aarch64_simd_vect_par_cnst_half, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-11-06 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half): Take the number of units too. * config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise. (aarch64_simd_check_vect_par_cnst_half): Update call accordingly, but check for a vector mode before rather than after the call. * config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>) (move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>) (vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>) (vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>) (vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>) (aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3) (widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>) (aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>) (aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>) (aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>) (aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>) (aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>) (aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>) (aarch64_sqdmull2_n<mode>): Update accordingly. Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r254468
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
73e3da5163
commit
f5cbabc1cc
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@ -1,3 +1,27 @@
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2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
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Alan Hayward <alan.hayward@arm.com>
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David Sherwood <david.sherwood@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half):
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Take the number of units too.
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* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise.
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(aarch64_simd_check_vect_par_cnst_half): Update call accordingly,
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but check for a vector mode before rather than after the call.
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* config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>)
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(move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>)
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(vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>)
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(vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>)
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(vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>)
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(aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3)
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(widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>)
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(aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>)
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(aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>)
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(aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>)
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(aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>)
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(aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>)
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(aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>)
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(aarch64_sqdmull2_n<mode>): Update accordingly.
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2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
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Alan Hayward <alan.hayward@arm.com>
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David Sherwood <david.sherwood@arm.com>
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@ -391,7 +391,7 @@ const char *aarch64_output_move_struct (rtx *operands);
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rtx aarch64_return_addr (int, rtx);
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rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
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bool aarch64_simd_mem_operand_p (rtx);
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rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool);
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rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool);
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rtx aarch64_tls_get_addr (void);
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tree aarch64_fold_builtin (tree, int, tree *, bool);
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unsigned aarch64_dbx_register_number (unsigned);
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@ -253,8 +253,8 @@
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{
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rtx dst_low_part = gen_lowpart (<VHALF>mode, dst);
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rtx dst_high_part = gen_highpart (<VHALF>mode, dst);
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rtx lo = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx lo = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn
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(gen_aarch64_simd_mov_from_<mode>low (dst_low_part, src, lo));
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@ -1437,7 +1437,7 @@
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(match_operand:<VHALF> 1 "register_operand" "")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_simd_move_hi_quad_be_<mode> (operands[0],
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operands[1], p));
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@ -1521,7 +1521,7 @@
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(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_simd_vec_unpack<su>_hi_<mode> (operands[0],
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operands[1], p));
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DONE;
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@ -1533,7 +1533,7 @@
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(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand" ""))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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emit_insn (gen_aarch64_simd_vec_unpack<su>_lo_<mode> (operands[0],
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operands[1], p));
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DONE;
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@ -1653,7 +1653,7 @@
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(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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emit_insn (gen_aarch64_simd_vec_<su>mult_lo_<mode> (operands[0],
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operands[1],
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operands[2], p));
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@ -1680,7 +1680,7 @@
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(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_simd_vec_<su>mult_hi_<mode> (operands[0],
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operands[1],
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operands[2], p));
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@ -2084,7 +2084,7 @@
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(match_operand:VQ_HSF 1 "register_operand" "")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
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operands[1], p));
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DONE;
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@ -2107,7 +2107,7 @@
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(match_operand:VQ_HSF 1 "register_operand" "")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
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operands[1], p));
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DONE;
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@ -3028,7 +3028,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_saddl<mode>_hi_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3040,7 +3040,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_uaddl<mode>_hi_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3052,7 +3052,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_ssubl<mode>_hi_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3064,7 +3064,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_usubl<mode>_hi_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3090,7 +3090,7 @@
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(match_operand:<VDBLW> 2 "register_operand" "")))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
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emit_insn (gen_aarch64_saddw<mode>_internal (temp, operands[2],
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@ -3118,7 +3118,7 @@
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(match_operand:<VDBLW> 2 "register_operand" "")))]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
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rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
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emit_insn (gen_aarch64_uaddw<mode>_internal (temp, operands[2],
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@ -3179,7 +3179,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_saddw2<mode>_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3191,7 +3191,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_uaddw2<mode>_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3204,7 +3204,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_ssubw2<mode>_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3216,7 +3216,7 @@
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(match_operand:VQW 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_usubw2<mode>_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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@ -3736,7 +3736,7 @@
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(match_operand:VQ_HSI 3 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlal2<mode>_internal (operands[0], operands[1],
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operands[2], operands[3], p));
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DONE;
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@ -3749,7 +3749,7 @@
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(match_operand:VQ_HSI 3 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlsl2<mode>_internal (operands[0], operands[1],
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operands[2], operands[3], p));
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DONE;
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@ -3817,7 +3817,7 @@
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(match_operand:SI 4 "immediate_operand" "i")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], p));
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@ -3832,7 +3832,7 @@
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(match_operand:SI 4 "immediate_operand" "i")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlal2_laneq<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], p));
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@ -3847,7 +3847,7 @@
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(match_operand:SI 4 "immediate_operand" "i")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], p));
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@ -3862,7 +3862,7 @@
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(match_operand:SI 4 "immediate_operand" "i")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlsl2_laneq<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], p));
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@ -3895,7 +3895,7 @@
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(match_operand:<VEL> 3 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlal2_n<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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p));
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@ -3909,7 +3909,7 @@
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(match_operand:<VEL> 3 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmlsl2_n<mode>_internal (operands[0], operands[1],
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operands[2], operands[3],
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p));
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@ -4063,7 +4063,7 @@
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(match_operand:VQ_HSI 2 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_sqdmull2<mode>_internal (operands[0], operands[1],
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operands[2], p));
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DONE;
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|
@ -4124,7 +4124,7 @@
|
|||
(match_operand:SI 3 "immediate_operand" "i")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
|
||||
emit_insn (gen_aarch64_sqdmull2_lane<mode>_internal (operands[0], operands[1],
|
||||
operands[2], operands[3],
|
||||
p));
|
||||
|
|
@ -4138,7 +4138,7 @@
|
|||
(match_operand:SI 3 "immediate_operand" "i")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
|
||||
emit_insn (gen_aarch64_sqdmull2_laneq<mode>_internal (operands[0], operands[1],
|
||||
operands[2], operands[3],
|
||||
p));
|
||||
|
|
@ -4171,7 +4171,7 @@
|
|||
(match_operand:<VEL> 2 "register_operand" "w")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
|
||||
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
|
||||
emit_insn (gen_aarch64_sqdmull2_n<mode>_internal (operands[0], operands[1],
|
||||
operands[2], p));
|
||||
DONE;
|
||||
|
|
|
|||
|
|
@ -11757,12 +11757,12 @@ Architecture 3 2 1 0 3 2 1 0
|
|||
|
||||
Low Mask: { 2, 3 } { 0, 1 }
|
||||
High Mask: { 0, 1 } { 2, 3 }
|
||||
*/
|
||||
|
||||
MODE Is the mode of the vector and NUNITS is the number of units in it. */
|
||||
|
||||
rtx
|
||||
aarch64_simd_vect_par_cnst_half (machine_mode mode, bool high)
|
||||
aarch64_simd_vect_par_cnst_half (machine_mode mode, int nunits, bool high)
|
||||
{
|
||||
int nunits = GET_MODE_NUNITS (mode);
|
||||
rtvec v = rtvec_alloc (nunits / 2);
|
||||
int high_base = nunits / 2;
|
||||
int low_base = 0;
|
||||
|
|
@ -11791,14 +11791,15 @@ bool
|
|||
aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
|
||||
bool high)
|
||||
{
|
||||
rtx ideal = aarch64_simd_vect_par_cnst_half (mode, high);
|
||||
if (!VECTOR_MODE_P (mode))
|
||||
return false;
|
||||
|
||||
rtx ideal = aarch64_simd_vect_par_cnst_half (mode, GET_MODE_NUNITS (mode),
|
||||
high);
|
||||
HOST_WIDE_INT count_op = XVECLEN (op, 0);
|
||||
HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0);
|
||||
int i = 0;
|
||||
|
||||
if (!VECTOR_MODE_P (mode))
|
||||
return false;
|
||||
|
||||
if (count_op != count_ideal)
|
||||
return false;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue