From f5dcbee1652ffdfabb23d9a586a92ce79153bba3 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 4 Nov 2014 12:09:38 +0000 Subject: [PATCH] [ARM] Migrate to new reduc_[us](min|max)_scal_optab config/arm/neon.md (reduc_smin_ *2): Rename to... (reduc_smin_scal_ *2): ...this; extract scalar result. (reduc_smax_ *2): Rename to... (reduc_smax_scal_ *2): ...this; extract scalar result. (reduc_umin_ *2): Rename to... (reduc_umin_scal_ *2): ...this; extract scalar result. (reduc_umax_ *2): Rename to... (reduc_umax_scal_ *2): ...this; extract scalar result. From-SVN: r217080 --- gcc/ChangeLog | 11 +++++++ gcc/config/arm/neon.md | 69 ++++++++++++++++++++++-------------------- 2 files changed, 48 insertions(+), 32 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a2568e47b5f..0ecdd5b01fd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2014-11-04 Alan Lawrence + + config/arm/neon.md (reduc_smin_ *2): Rename to... + (reduc_smin_scal_ *2): ...this; extract scalar result. + (reduc_smax_ *2): Rename to... + (reduc_smax_scal_ *2): ...this; extract scalar result. + (reduc_umin_ *2): Rename to... + (reduc_umin_scal_ *2): ...this; extract scalar result. + (reduc_umax_ *2): Rename to... + (reduc_umax_scal_ *2): ...this; extract scalar result. + 2014-11-04 Alan Lawrence config/arm/neon.md (reduc_plus_*): Rename to... diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 48270157715..e7f5abe5aec 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1398,104 +1398,109 @@ [(set_attr "type" "neon_add_q")] ) -(define_expand "reduc_smin_" - [(match_operand:VD 0 "s_register_operand" "") +(define_expand "reduc_smin_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VD 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" { - neon_pairwise_reduce (operands[0], operands[1], mode, + rtx vec = gen_reg_rtx (mode); + + neon_pairwise_reduce (vec, operands[1], mode, &gen_neon_vpsmin); + /* The result is computed into every element of the vector. */ + emit_insn (gen_vec_extract (operands[0], vec, const0_rtx)); DONE; }) -(define_expand "reduc_smin_" - [(match_operand:VQ 0 "s_register_operand" "") +(define_expand "reduc_smin_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VQ 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (mode); - rtx res_d = gen_reg_rtx (mode); emit_insn (gen_quad_halves_smin (step1, operands[1])); - emit_insn (gen_reduc_smin_ (res_d, step1)); - emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + emit_insn (gen_reduc_smin_scal_ (operands[0], step1)); DONE; }) -(define_expand "reduc_smax_" - [(match_operand:VD 0 "s_register_operand" "") +(define_expand "reduc_smax_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VD 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" { - neon_pairwise_reduce (operands[0], operands[1], mode, + rtx vec = gen_reg_rtx (mode); + neon_pairwise_reduce (vec, operands[1], mode, &gen_neon_vpsmax); + /* The result is computed into every element of the vector. */ + emit_insn (gen_vec_extract (operands[0], vec, const0_rtx)); DONE; }) -(define_expand "reduc_smax_" - [(match_operand:VQ 0 "s_register_operand" "") +(define_expand "reduc_smax_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VQ 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (mode); - rtx res_d = gen_reg_rtx (mode); emit_insn (gen_quad_halves_smax (step1, operands[1])); - emit_insn (gen_reduc_smax_ (res_d, step1)); - emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + emit_insn (gen_reduc_smax_scal_ (operands[0], step1)); DONE; }) -(define_expand "reduc_umin_" - [(match_operand:VDI 0 "s_register_operand" "") +(define_expand "reduc_umin_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VDI 1 "s_register_operand" "")] "TARGET_NEON" { - neon_pairwise_reduce (operands[0], operands[1], mode, + rtx vec = gen_reg_rtx (mode); + neon_pairwise_reduce (vec, operands[1], mode, &gen_neon_vpumin); + /* The result is computed into every element of the vector. */ + emit_insn (gen_vec_extract (operands[0], vec, const0_rtx)); DONE; }) -(define_expand "reduc_umin_" - [(match_operand:VQI 0 "s_register_operand" "") +(define_expand "reduc_umin_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VQI 1 "s_register_operand" "")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (mode); - rtx res_d = gen_reg_rtx (mode); emit_insn (gen_quad_halves_umin (step1, operands[1])); - emit_insn (gen_reduc_umin_ (res_d, step1)); - emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + emit_insn (gen_reduc_umin_scal_ (operands[0], step1)); DONE; }) -(define_expand "reduc_umax_" - [(match_operand:VDI 0 "s_register_operand" "") +(define_expand "reduc_umax_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VDI 1 "s_register_operand" "")] "TARGET_NEON" { - neon_pairwise_reduce (operands[0], operands[1], mode, + rtx vec = gen_reg_rtx (mode); + neon_pairwise_reduce (vec, operands[1], mode, &gen_neon_vpumax); + /* The result is computed into every element of the vector. */ + emit_insn (gen_vec_extract (operands[0], vec, const0_rtx)); DONE; }) -(define_expand "reduc_umax_" - [(match_operand:VQI 0 "s_register_operand" "") +(define_expand "reduc_umax_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VQI 1 "s_register_operand" "")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (mode); - rtx res_d = gen_reg_rtx (mode); emit_insn (gen_quad_halves_umax (step1, operands[1])); - emit_insn (gen_reduc_umax_ (res_d, step1)); - emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + emit_insn (gen_reduc_umax_scal_ (operands[0], step1)); DONE; })