[amdgcn] Use first lane of v1 for zero offset
Use v1 instead of v0 when a zero-valued VGPR is needed. This frees up v0 for other purposes. 2019-11-15 Kwok Cheung Yeung <kcy@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_expand_prologue): Remove initialization and prologue use of v0. (print_operand_address): Use v1 for zero vector offset. From-SVN: r278297
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@ -1,3 +1,10 @@
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2019-11-15 Kwok Cheung Yeung <kcy@codesourcery.com>
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gcc/
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* config/gcn/gcn.c (gcn_expand_prologue): Remove initialization and
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prologue use of v0.
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(print_operand_address): Use v1 for zero vector offset.
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2019-11-15 Richard Sandiford <richard.sandiford@arm.com>
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PR tree-optimization/92515
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@ -2803,15 +2803,6 @@ gcn_expand_prologue ()
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cfun->machine->args.
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reg[PRIVATE_SEGMENT_WAVE_OFFSET_ARG]);
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if (TARGET_GCN5_PLUS)
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{
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/* v0 is reserved for constant zero so that "global"
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memory instructions can have a nul-offset without
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causing reloads. */
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emit_insn (gen_vec_duplicatev64si
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(gen_rtx_REG (V64SImode, VGPR_REGNO (0)), const0_rtx));
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}
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if (cfun->machine->args.requested & (1 << FLAT_SCRATCH_INIT_ARG))
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{
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rtx fs_init_lo =
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@ -2870,8 +2861,6 @@ gcn_expand_prologue ()
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gen_int_mode (LDS_SIZE, SImode));
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emit_insn (gen_prologue_use (gen_rtx_REG (SImode, M0_REG)));
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if (TARGET_GCN5_PLUS)
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emit_insn (gen_prologue_use (gen_rtx_REG (SImode, VGPR_REGNO (0))));
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if (cfun && cfun->machine && !cfun->machine->normal_function && flag_openmp)
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{
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@ -5327,9 +5316,9 @@ print_operand_address (FILE *file, rtx mem)
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/* The assembler requires a 64-bit VGPR pair here, even though
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the offset should be only 32-bit. */
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if (vgpr_offset == NULL_RTX)
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/* In this case, the vector offset is zero, so we use v0,
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which is initialized by the kernel prologue to zero. */
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fprintf (file, "v[0:1]");
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/* In this case, the vector offset is zero, so we use the first
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lane of v1, which is initialized to zero. */
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fprintf (file, "v[1:2]");
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else if (REG_P (vgpr_offset)
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&& VGPR_REGNO_P (REGNO (vgpr_offset)))
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{
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