pa.h (VAL_U6_BITS_P): Define.
* config/pa/pa.h (VAL_U6_BITS_P): Define. (INT_U6_BITS): Likewise. * config/pa/predicates.md (uint6_operand): New predicate. (shift5_operand, shift6_operand): Likewise. * config/pa/pa.md (lshrsi3, rotrsi3): Use shift5_operand instead of arith32_operand. (lshrdi3): Use shift6_operand. (shrpsi4, shrpdi4): New insn patterns. (extzv): Delete expander. (extzvsi, extzvdi): New expanders. Use uint5_operand and uint6_operand predicates in unamed zero extract patterns. Tighten common constraint. (extv): Delete expander. (extvsi, extvdi): New expanders. Use uint5_operand and uint6_operand predicates in unamed sign extract patterns. Tighten common constraint. (insv): Delete expander. (insvsi, insvdi): New expanders. Use uint5_operand and uint6_operand predicates in unamed insert patterns. Tighten common constraint. Change uint32_operand predicate to uint6_operand predicate in unamed DImode pattern to insert constant values of type 1...1xxxx. From-SVN: r195045
This commit is contained in:
John David Anglin
John David Anglin
parent
2a4e207b71
commit
f6f94d948b
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@ -1,3 +1,25 @@
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2013-01-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* config/pa/pa.h (VAL_U6_BITS_P): Define.
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(INT_U6_BITS): Likewise.
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* config/pa/predicates.md (uint6_operand): New predicate.
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(shift5_operand, shift6_operand): Likewise.
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* config/pa/pa.md (lshrsi3, rotrsi3): Use shift5_operand instead of
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arith32_operand.
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(lshrdi3): Use shift6_operand.
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(shrpsi4, shrpdi4): New insn patterns.
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(extzv): Delete expander.
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(extzvsi, extzvdi): New expanders. Use uint5_operand and uint6_operand
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predicates in unamed zero extract patterns. Tighten common constraint.
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(extv): Delete expander.
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(extvsi, extvdi): New expanders. Use uint5_operand and uint6_operand
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predicates in unamed sign extract patterns. Tighten common constraint.
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(insv): Delete expander.
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(insvsi, insvdi): New expanders. Use uint5_operand and uint6_operand
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predicates in unamed insert patterns. Tighten common constraint.
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Change uint32_operand predicate to uint6_operand predicate in unamed
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DImode pattern to insert constant values of type 1...1xxxx.
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2013-01-04 Jan Hubicka <jh@suse.cz>
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PR tree-optimization/55823
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@ -956,6 +956,9 @@ extern int may_call_alloca;
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#define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
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#define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
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#define VAL_U6_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x40)
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#define INT_U6_BITS(X) VAL_U6_BITS_P (INTVAL (X))
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#define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
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#define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
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@ -6584,7 +6584,7 @@
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "arith32_operand" "q,n")))]
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(match_operand:SI 2 "shift5_operand" "q,n")))]
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""
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"@
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{vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
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@ -6595,7 +6595,7 @@
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(define_insn "lshrdi3"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
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(match_operand:DI 2 "arith32_operand" "q,n")))]
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(match_operand:DI 2 "shift6_operand" "q,n")))]
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"TARGET_64BIT"
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"@
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shrpd %%r0,%1,%%sar,%0
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@ -6603,10 +6603,40 @@
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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; Shift right pair word 0 to 31 bits.
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(define_insn "shrpsi4"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
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(minus:SI (const_int 32)
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(match_operand:SI 3 "shift5_operand" "q,n")))
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(lshiftrt:SI (match_operand:SI 2 "register_operand" "r,r")
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(match_dup 3))))]
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""
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"@
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{vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}
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{shd|shrpw} %1,%2,%3,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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; Shift right pair doubleword 0 to 63 bits.
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(define_insn "shrpdi4"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(ior:DI (ashift:DI (match_operand:SI 1 "register_operand" "r,r")
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(minus:DI (const_int 64)
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(match_operand:DI 3 "shift6_operand" "q,n")))
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(lshiftrt:DI (match_operand:DI 2 "register_operand" "r,r")
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(match_dup 3))))]
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"TARGET_64BIT"
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"@
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shrpd %1,%2,%%sar,%0
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shrpd %1,%2,%3,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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(define_insn "rotrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "arith32_operand" "q,n")))]
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(match_operand:SI 2 "shift5_operand" "q,n")))]
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""
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"*
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{
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@ -8365,21 +8395,22 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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}")
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;;; Operands 2 and 3 are assumed to be CONST_INTs.
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(define_expand "extzv"
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[(set (match_operand 0 "register_operand" "")
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(zero_extract (match_operand 1 "register_operand" "")
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(match_operand 2 "uint32_operand" "")
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(match_operand 3 "uint32_operand" "")))]
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(define_expand "extzvsi"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"
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{
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HOST_WIDE_INT len = INTVAL (operands[2]);
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HOST_WIDE_INT pos = INTVAL (operands[3]);
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unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
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unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
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/* PA extraction insns don't support zero length bitfields or fields
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extending beyond the left or right-most bits. Also, we reject lengths
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equal to a word as they are better handled by the move patterns. */
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if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
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extending beyond the left or right-most bits. Also, the predicate
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rejects lengths equal to a word as they are better handled by
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the move patterns. */
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if (len == 0 || pos + len > 32)
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FAIL;
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/* From mips.md: extract_bit_field doesn't verify that our source
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@ -8387,12 +8418,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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if (!register_operand (operands[1], VOIDmode))
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FAIL;
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if (TARGET_64BIT)
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emit_insn (gen_extzv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_extzv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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emit_insn (gen_extzv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}")
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@ -8401,7 +8428,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"UINTVAL (operands[2]) > 0
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&& UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
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"{extru|extrw,u} %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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@ -8416,12 +8444,42 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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(define_expand "extzvdi"
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extract:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "uint6_operand" "")
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(match_operand:DI 3 "uint6_operand" "")))]
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"TARGET_64BIT"
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"
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{
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unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
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unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
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/* PA extraction insns don't support zero length bitfields or fields
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extending beyond the left or right-most bits. Also, the predicate
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rejects lengths equal to a doubleword as they are better handled by
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the move patterns. */
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if (len == 0 || pos + len > 64)
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FAIL;
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/* From mips.md: extract_bit_field doesn't verify that our source
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matches the predicate, so check it again here. */
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if (!register_operand (operands[1], VOIDmode))
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FAIL;
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emit_insn (gen_extzv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}")
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(define_insn "extzv_64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extract:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "uint32_operand" "")
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(match_operand:DI 3 "uint32_operand" "")))]
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"TARGET_64BIT"
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(match_operand:DI 2 "uint6_operand" "")
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(match_operand:DI 3 "uint6_operand" "")))]
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"TARGET_64BIT
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&& UINTVAL (operands[2]) > 0
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&& UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
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"extrd,u %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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@ -8437,21 +8495,22 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(set_attr "length" "4")])
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;;; Operands 2 and 3 are assumed to be CONST_INTs.
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(define_expand "extv"
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[(set (match_operand 0 "register_operand" "")
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(sign_extract (match_operand 1 "register_operand" "")
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(match_operand 2 "uint32_operand" "")
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(match_operand 3 "uint32_operand" "")))]
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(define_expand "extvsi"
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[(set (match_operand:SI 0 "register_operand" "")
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(sign_extract:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"
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{
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HOST_WIDE_INT len = INTVAL (operands[2]);
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HOST_WIDE_INT pos = INTVAL (operands[3]);
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unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
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unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
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/* PA extraction insns don't support zero length bitfields or fields
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extending beyond the left or right-most bits. Also, we reject lengths
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equal to a word as they are better handled by the move patterns. */
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if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
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extending beyond the left or right-most bits. Also, the predicate
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rejects lengths equal to a word as they are better handled by
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the move patterns. */
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if (len == 0 || pos + len > 32)
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FAIL;
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/* From mips.md: extract_bit_field doesn't verify that our source
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@ -8459,12 +8518,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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if (!register_operand (operands[1], VOIDmode))
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FAIL;
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if (TARGET_64BIT)
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emit_insn (gen_extv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_extv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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emit_insn (gen_extv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}")
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@ -8473,7 +8528,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"UINTVAL (operands[2]) > 0
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&& UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
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"{extrs|extrw,s} %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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@ -8488,12 +8544,42 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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(define_expand "extvdi"
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[(set (match_operand:DI 0 "register_operand" "")
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(sign_extract:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "uint6_operand" "")
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(match_operand:DI 3 "uint6_operand" "")))]
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"TARGET_64BIT"
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"
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{
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unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
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unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
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/* PA extraction insns don't support zero length bitfields or fields
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extending beyond the left or right-most bits. Also, the predicate
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rejects lengths equal to a doubleword as they are better handled by
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the move patterns. */
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if (len == 0 || pos + len > 64)
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FAIL;
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/* From mips.md: extract_bit_field doesn't verify that our source
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matches the predicate, so check it again here. */
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if (!register_operand (operands[1], VOIDmode))
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FAIL;
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emit_insn (gen_extv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}")
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(define_insn "extv_64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extract:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "uint32_operand" "")
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(match_operand:DI 3 "uint32_operand" "")))]
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"TARGET_64BIT"
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(match_operand:DI 2 "uint6_operand" "")
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(match_operand:DI 3 "uint6_operand" "")))]
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"TARGET_64BIT
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&& UINTVAL (operands[2]) > 0
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&& UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
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"extrd,s %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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|
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@ -8509,21 +8595,22 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(set_attr "length" "4")])
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;;; Operands 1 and 2 are assumed to be CONST_INTs.
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(define_expand "insv"
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[(set (zero_extract (match_operand 0 "register_operand" "")
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(match_operand 1 "uint32_operand" "")
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(match_operand 2 "uint32_operand" ""))
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(match_operand 3 "arith5_operand" ""))]
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(define_expand "insvsi"
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[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "uint5_operand" "")
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(match_operand:SI 2 "uint5_operand" ""))
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(match_operand:SI 3 "arith5_operand" ""))]
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""
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"
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{
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HOST_WIDE_INT len = INTVAL (operands[1]);
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HOST_WIDE_INT pos = INTVAL (operands[2]);
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unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
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unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
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/* PA insertion insns don't support zero length bitfields or fields
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extending beyond the left or right-most bits. Also, we reject lengths
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equal to a word as they are better handled by the move patterns. */
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if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
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extending beyond the left or right-most bits. Also, the predicate
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rejects lengths equal to a word as they are better handled by
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the move patterns. */
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if (len <= 0 || pos + len > 32)
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FAIL;
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/* From mips.md: insert_bit_field doesn't verify that our destination
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@ -8531,12 +8618,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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if (!register_operand (operands[0], VOIDmode))
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FAIL;
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if (TARGET_64BIT)
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emit_insn (gen_insv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_insv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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emit_insn (gen_insv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}")
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@ -8545,7 +8628,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(match_operand:SI 1 "uint5_operand" "")
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(match_operand:SI 2 "uint5_operand" ""))
|
||||
(match_operand:SI 3 "arith5_operand" "r,L"))]
|
||||
""
|
||||
"UINTVAL (operands[1]) > 0
|
||||
&& UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
|
||||
"@
|
||||
{dep|depw} %3,%2+%1-1,%1,%0
|
||||
{depi|depwi} %3,%2+%1-1,%1,%0"
|
||||
|
|
@ -8568,12 +8652,42 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
|
|||
[(set_attr "type" "shift")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_expand "insvdi"
|
||||
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "uint6_operand" "")
|
||||
(match_operand:DI 2 "uint6_operand" ""))
|
||||
(match_operand:DI 3 "arith5_operand" ""))]
|
||||
"TARGET_64BIT"
|
||||
"
|
||||
{
|
||||
unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
|
||||
unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
|
||||
|
||||
/* PA insertion insns don't support zero length bitfields or fields
|
||||
extending beyond the left or right-most bits. Also, the predicate
|
||||
rejects lengths equal to a doubleword as they are better handled by
|
||||
the move patterns. */
|
||||
if (len <= 0 || pos + len > 64)
|
||||
FAIL;
|
||||
|
||||
/* From mips.md: insert_bit_field doesn't verify that our destination
|
||||
matches the predicate, so check it again here. */
|
||||
if (!register_operand (operands[0], VOIDmode))
|
||||
FAIL;
|
||||
|
||||
emit_insn (gen_insv_64 (operands[0], operands[1],
|
||||
operands[2], operands[3]));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_insn "insv_64"
|
||||
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
|
||||
(match_operand:DI 1 "uint32_operand" "")
|
||||
(match_operand:DI 2 "uint32_operand" ""))
|
||||
(match_operand:DI 3 "arith32_operand" "r,L"))]
|
||||
"TARGET_64BIT"
|
||||
(match_operand:DI 1 "uint6_operand" "")
|
||||
(match_operand:DI 2 "uint6_operand" ""))
|
||||
(match_operand:DI 3 "arith5_operand" "r,L"))]
|
||||
"TARGET_64BIT
|
||||
&& UINTVAL (operands[1]) > 0
|
||||
&& UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 64"
|
||||
"@
|
||||
depd %3,%2+%1-1,%1,%0
|
||||
depdi %3,%2+%1-1,%1,%0"
|
||||
|
|
@ -8583,8 +8697,8 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
|
|||
;; Optimize insertion of const_int values of type 1...1xxxx.
|
||||
(define_insn ""
|
||||
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
|
||||
(match_operand:DI 1 "uint32_operand" "")
|
||||
(match_operand:DI 2 "uint32_operand" ""))
|
||||
(match_operand:DI 1 "uint6_operand" "")
|
||||
(match_operand:DI 2 "uint6_operand" ""))
|
||||
(match_operand:DI 3 "const_int_operand" ""))]
|
||||
"(INTVAL (operands[3]) & 0x10) != 0
|
||||
&& TARGET_64BIT
|
||||
|
|
|
|||
|
|
@ -31,6 +31,13 @@
|
|||
(and (match_code "const_int")
|
||||
(match_test "INT_U5_BITS (op)")))
|
||||
|
||||
;; Return truth value of whether OP is an integer which fits the range
|
||||
;; constraining 6-bit unsigned immediate operands in three-address insns.
|
||||
|
||||
(define_predicate "uint6_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "INT_U6_BITS (op)")))
|
||||
|
||||
;; Return truth value of whether OP is an integer which fits the range
|
||||
;; constraining 11-bit signed immediate operands in three-address insns.
|
||||
|
||||
|
|
@ -125,6 +132,20 @@
|
|||
(ior (match_operand 0 "register_operand")
|
||||
(match_code "const_int")))
|
||||
|
||||
;; Return truth value of whether OP can be used as a shift operand in
|
||||
;; a shift insn that accepts registers of mode MODE or 5-bit shift amounts.
|
||||
|
||||
(define_predicate "shift5_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "uint5_operand")))
|
||||
|
||||
;; Return truth value of whether OP can be used as a shift operand in
|
||||
;; a shift insn that accepts registers of mode MODE or 6-bit shift amounts.
|
||||
|
||||
(define_predicate "shift6_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "uint6_operand")))
|
||||
|
||||
;; True iff OP can be used as an operand in an adddi3 insn.
|
||||
|
||||
(define_predicate "adddi3_operand"
|
||||
|
|
|
|||
Loading…
Reference in New Issue