sparc.c (sparc_emit_set_const64_quick2, [...]): Fix more bugs in 64-bit constant formation.
* config/sparc/sparc.c (sparc_emit_set_const64_quick2, sparc_emit_set_const64_longway, const64_is_2insns, create_simple_focus_bits, sparc_emit_set_const64): Fix more bugs in 64-bit constant formation. * config/sparc/sparc.md (snesi_zero_extend split): Generate rtl for addx not subx. (define_insn movdi_const64_special): Make available even when HOST_BITS_PER_WIDE_INT is not 64. (movdi_lo_sum_sp64_cint, movdi_high_sp64_cint): Remove. (losum_di_medlow, sethm, setlo): Make op2 symbolic_operand. (cmp_siqi_trunc_set, cmp_diqi_trunc_set): Encapsulate both instances of operand 1 inside a QI subreg. (xordi3_sp64_dbl): Remove '%' constraint for op1. (one_cmpldi2_sp64): Fix output string. (one_cmplsi2_not_liveg0): Rewrite to remove unneeded extra alternative case. (unnamed arch64 ashift DI): Truncate shift count if greater than 63, not 31. From-SVN: r21733
This commit is contained in:
David S. Miller
David S. Miller
parent
6036acbbf2
commit
f710f868cb
@ -1,3 +1,24 @@
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Fri Aug 14 12:58:21 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.c (sparc_emit_set_const64_quick2,
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sparc_emit_set_const64_longway, const64_is_2insns,
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create_simple_focus_bits, sparc_emit_set_const64): Fix more bugs
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in 64-bit constant formation.
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* config/sparc/sparc.md (snesi_zero_extend split): Generate
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rtl for addx not subx.
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(define_insn movdi_const64_special): Make available even when
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HOST_BITS_PER_WIDE_INT is not 64.
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(movdi_lo_sum_sp64_cint, movdi_high_sp64_cint): Remove.
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(losum_di_medlow, sethm, setlo): Make op2 symbolic_operand.
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(cmp_siqi_trunc_set, cmp_diqi_trunc_set): Encapsulate both
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instances of operand 1 inside a QI subreg.
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(xordi3_sp64_dbl): Remove '%' constraint for op1.
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(one_cmpldi2_sp64): Fix output string.
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(one_cmplsi2_not_liveg0): Rewrite to remove unneeded extra
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alternative case.
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(unnamed arch64 ashift DI): Truncate shift count if greater than
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63, not 31.
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Fri Aug 14 21:52:53 1998 J"orn Rennecke <amylaar@cygnus.co.uk>
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* expr.c (store_expr): Don't optimize away load-store pair
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@ -1229,7 +1229,7 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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{
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/* Getting this right wrt. reloading is really tricky.
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We _MUST_ have a seperate temporary at this point,
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if we don't barf immediately instead of generating
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so we barf immediately instead of generating
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incorrect code. */
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if (temp1 == op0)
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abort ();
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@ -1369,7 +1369,7 @@ sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
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}
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else
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{
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emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high_bits)));
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emit_insn (gen_safe_SET64 (temp, high_bits));
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temp2 = temp;
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}
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@ -1416,7 +1416,7 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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}
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else
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{
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emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high_bits)));
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emit_insn (gen_safe_SET64 (temp, high_bits));
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sub_temp = temp;
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}
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@ -1432,10 +1432,17 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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sparc_emit_set_safe_HIGH64 (temp2, low_bits);
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if ((low_bits & ~0xfffffc00) != 0)
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emit_insn (gen_rtx_SET (VOIDmode, temp3,
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gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_PLUS (DImode, temp4, temp3)));
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{
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emit_insn (gen_rtx_SET (VOIDmode, temp3,
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gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_PLUS (DImode, temp4, temp3)));
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}
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else
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{
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emit_insn (gen_rtx_SET (VOIDmode, op0,
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gen_rtx_PLUS (DImode, temp4, temp2)));
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}
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}
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else
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{
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@ -1572,17 +1579,14 @@ const64_is_2insns (high_bits, low_bits)
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&highest_bit_set, &lowest_bit_set,
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&all_bits_between_are_set);
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if (highest_bit_set == 63
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if ((highest_bit_set == 63
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|| lowest_bit_set == 0)
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&& all_bits_between_are_set != 0)
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return 1;
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if ((highest_bit_set - lowest_bit_set) < 21)
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return 1;
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if (high_bits == 0
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|| high_bits == 0xffffffff)
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return 1;
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return 0;
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}
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@ -1595,7 +1599,7 @@ create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set,
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unsigned HOST_WIDE_INT high_bits, low_bits;
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int highest_bit_set, lowest_bit_set, shift;
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{
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int hi, lo;
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HOST_WIDE_INT hi, lo;
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if (lowest_bit_set < 32)
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{
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@ -1634,13 +1638,14 @@ sparc_emit_set_const64 (op0, op1)
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&& REGNO (op0) <= SPARC_LAST_V9_FP_REG))
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abort ();
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if (reload_in_progress || reload_completed)
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temp = op0;
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else
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temp = gen_reg_rtx (DImode);
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if (GET_CODE (op1) != CONST_DOUBLE
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&& GET_CODE (op1) != CONST_INT)
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{
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if (reload_in_progress || reload_completed)
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temp = op0;
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else
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temp = gen_reg_rtx (DImode);
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sparc_emit_set_symbolic_const64 (op0, op1, temp);
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return;
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}
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@ -1671,11 +1676,6 @@ sparc_emit_set_const64 (op0, op1)
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/* low_bits bits 0 --> 31
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high_bits bits 32 --> 63 */
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if (reload_in_progress || reload_completed)
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temp = op0;
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else
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temp = gen_reg_rtx (DImode);
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analyze_64bit_constant (high_bits, low_bits,
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&highest_bit_set, &lowest_bit_set,
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&all_bits_between_are_set);
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@ -1699,15 +1699,9 @@ sparc_emit_set_const64 (op0, op1)
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HOST_WIDE_INT the_const = -1;
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int shift = lowest_bit_set;
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if (highest_bit_set == lowest_bit_set)
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{
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/* There is no way to get here like this, because this case
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can be done in one instruction. */
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if (lowest_bit_set < 32)
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abort ();
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the_const = 1;
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}
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else if (all_bits_between_are_set == 0)
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if ((highest_bit_set != 63
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&& lowest_bit_set != 0)
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|| all_bits_between_are_set == 0)
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{
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the_const =
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create_simple_focus_bits (high_bits, low_bits,
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@ -1717,6 +1711,9 @@ sparc_emit_set_const64 (op0, op1)
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else if (lowest_bit_set == 0)
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shift = -(63 - highest_bit_set);
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if (! SPARC_SIMM13_P (the_const))
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abort ();
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emit_insn (gen_safe_SET64 (temp, the_const));
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if (shift > 0)
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emit_insn (gen_rtx_SET (VOIDmode,
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@ -1746,6 +1743,10 @@ sparc_emit_set_const64 (op0, op1)
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unsigned HOST_WIDE_INT focus_bits =
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create_simple_focus_bits (high_bits, low_bits,
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highest_bit_set, lowest_bit_set, 10);
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if (! SPARC_SETHI_P (focus_bits))
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abort ();
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sparc_emit_set_safe_HIGH64 (temp, focus_bits);
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/* If lowest_bit_set == 10 then a sethi alone could have done it. */
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@ -1777,20 +1778,20 @@ sparc_emit_set_const64 (op0, op1)
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return;
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}
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/* Now, try 3-insn sequences. */
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/* 1) sethi %hi(high_bits), %reg
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* or %reg, %lo(high_bits), %reg
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* sllx %reg, 32, %reg
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*/
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if (low_bits == 0
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|| (SPARC_SIMM13_P(low_bits)
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&& ((HOST_WIDE_INT)low_bits > 0)))
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if (low_bits == 0)
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{
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sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
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sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
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return;
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}
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/* Now, try 3-insn sequences. But first we may be able to do something
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quick when the constant is negated, so try that. */
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/* We may be able to do something quick
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when the constant is negated, so try that. */
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if (const64_is_2insns ((~high_bits) & 0xffffffff,
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(~low_bits) & 0xfffffc00))
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{
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@ -1832,10 +1833,15 @@ sparc_emit_set_const64 (op0, op1)
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/* 1) sethi %hi(xxx), %reg
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* or %reg, %lo(xxx), %reg
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* sllx %reg, yyy, %reg
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*
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* ??? This is just a generalized version of the low_bits==0
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* thing above, FIXME...
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*/
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if ((highest_bit_set - lowest_bit_set) < 32)
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{
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unsigned HOST_WIDE_INT hi, lo, focus_bits;
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unsigned HOST_WIDE_INT focus_bits =
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create_simple_focus_bits (high_bits, low_bits,
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highest_bit_set, lowest_bit_set, 0);
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/* We can't get here in this state. */
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if (highest_bit_set < 32
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@ -1844,17 +1850,24 @@ sparc_emit_set_const64 (op0, op1)
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/* So what we know is that the set bits straddle the
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middle of the 64-bit word. */
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hi = (low_bits >> lowest_bit_set);
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lo = (high_bits << (32 - lowest_bit_set));
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if (hi & lo)
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abort ();
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focus_bits = (hi | lo);
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sparc_emit_set_const64_quick2 (op0, temp,
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focus_bits, 0,
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lowest_bit_set);
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return;
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}
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/* 1) sethi %hi(high_bits), %reg
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* or %reg, %lo(high_bits), %reg
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* sllx %reg, 32, %reg
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* or %reg, low_bits, %reg
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*/
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if (SPARC_SIMM13_P(low_bits)
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&& ((int)low_bits > 0))
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{
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sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
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return;
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}
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/* The easiest way when all else fails, is full decomposition. */
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#if 0
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printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
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@ -1097,10 +1097,10 @@
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&& reload_completed"
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[(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
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(const_int 0)))
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(set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
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(const_int 0))
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(ltu:SI (reg:CC_NOOV 100)
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(const_int 0)))))]
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(set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
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(const_int 0))
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(ltu:SI (reg:CC_NOOV 100)
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(const_int 0)))))]
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"")
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(define_insn "*snedi_zero"
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@ -2332,6 +2332,7 @@
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[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
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(set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
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;; The following are generated by sparc_emit_set_const64
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(define_insn "*movdi_sp64_dbl"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "const64_operand" ""))]
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@ -2341,11 +2342,12 @@
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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;; This is needed to show CSE exactly which bits are set
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;; in a 64-bit register by sethi instructions.
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(define_insn "*movdi_const64_special"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "const64_high_operand" ""))]
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"(TARGET_ARCH64
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&& HOST_BITS_PER_WIDE_INT != 64)"
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"TARGET_ARCH64"
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"sethi\\t%%hi(%a1), %0"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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@ -2368,24 +2370,6 @@
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[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
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(set_attr "length" "1")])
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;; The following are generated by sparc_emit_set_const64
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(define_insn "*movdi_lo_sum_sp64_cint"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "const_int_operand" "in")))]
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"TARGET_ARCH64"
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"or\\t%1, %%lo(%a2), %0"
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[(set_attr "type" "ialu")
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(set_attr "length" "1")])
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(define_insn "*movdi_high_sp64_cint"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (match_operand:DI 1 "const_int_operand" "in")))]
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"TARGET_ARCH64"
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"sethi\\t%%hi(%a1), %0"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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;; ??? revisit this...
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(define_insn "move_label_di"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -2439,7 +2423,7 @@
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(define_insn "*losum_di_medlow"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "" "")))]
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(match_operand:DI 2 "symbolic_operand" "")))]
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"TARGET_CM_MEDLOW"
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"or\\t%1, %%lo(%a2), %0"
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[(set_attr "length" "1")])
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@ -2488,7 +2472,7 @@
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(define_insn "sethm"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(unspec:DI [(match_operand:DI 2 "" "")] 18)))]
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(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
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"TARGET_CM_MEDANY"
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"or\\t%1, %%hm(%a2), %0"
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[(set_attr "length" "1")])
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@ -2496,7 +2480,7 @@
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(define_insn "setlo"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "" "")))]
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(match_operand:DI 2 "symbolic_operand" "")))]
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"TARGET_CM_MEDANY"
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"or\\t%1, %%lo(%a2), %0"
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[(set_attr "length" "1")])
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@ -3915,7 +3899,7 @@
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(compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0)
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(const_int 0)))
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(set (match_operand:QI 0 "register_operand" "=r")
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(match_dup 1))]
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(subreg:QI (match_dup 1) 0))]
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""
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"andcc\\t%1, 0xff, %0"
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[(set_attr "type" "compare")
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@ -3935,7 +3919,7 @@
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(compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0)
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(const_int 0)))
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(set (match_operand:QI 0 "register_operand" "=r")
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(match_dup 1))]
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(subreg:QI (match_dup 1) 0))]
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"TARGET_ARCH64"
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"andcc\\t%1, 0xff, %0"
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[(set_attr "type" "compare")
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@ -4149,7 +4133,7 @@
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(GET_CODE (operands[2]) == CONST_INT
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? INTVAL (operands[2])
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: CONST_DOUBLE_LOW (operands[2])) - len;
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unsigned mask = ((1 << len) - 1) << pos;
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HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
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operands[1] = GEN_INT (mask);
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return \"andcc\\t%0, %1, %%g0\";
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@ -4178,7 +4162,7 @@
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(GET_CODE (operands[2]) == CONST_INT
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? INTVAL (operands[2])
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: CONST_DOUBLE_LOW (operands[2])) - len;
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unsigned HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
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HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
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operands[1] = GEN_INT (mask);
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return \"andcc\\t%0, %1, %%g0\";
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@ -5644,7 +5628,7 @@
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(define_insn "*xordi3_sp64_dbl"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(xor:DI (match_operand:DI 1 "register_operand" "%r")
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(xor:DI (match_operand:DI 1 "register_operand" "r")
|
||||
(match_operand:DI 2 "const64_operand" "")))]
|
||||
"(TARGET_ARCH64
|
||||
&& HOST_BITS_PER_WIDE_INT != 64)"
|
||||
@ -6058,7 +6042,7 @@
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")))]
|
||||
"TARGET_ARCH64"
|
||||
"xnor\\t%1, 0, %0"
|
||||
"xnor\\t%%g0, %1, %0"
|
||||
[(set_attr "type" "unary")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
@ -6085,15 +6069,14 @@
|
||||
}")
|
||||
|
||||
(define_insn "*one_cmplsi2_not_liveg0"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,d")
|
||||
(not:SI (match_operand:SI 1 "arith_operand" "r,I,d")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,d")
|
||||
(not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
|
||||
"! TARGET_LIVE_G0"
|
||||
"@
|
||||
xnor\\t%1, 0, %0
|
||||
xnor\\t%%g0, %1, %0
|
||||
fnot1s\\t%1, %0"
|
||||
[(set_attr "type" "unary,unary,fp")
|
||||
(set_attr "length" "1,1,1")])
|
||||
[(set_attr "type" "unary,fp")
|
||||
(set_attr "length" "1,1")])
|
||||
|
||||
(define_insn "*one_cmplsi2_liveg0"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,d")
|
||||
@ -6434,7 +6417,7 @@
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
|
||||
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
|
||||
|
||||
return \"sllx\\t%1, %2, %0\";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user