Test for _AM29K and _IBMR2, not ___AM29K__ and ___IBMR2__.
(arm umul_ppmm): New definition. (clipper umul_ppmm, smul_ppmm, __umulsidi3): New definitions. (hppa count_leading_zeros): New definition. (i960 umul_ppmm, __umulsidi3): New definitions. (mc68000 umul_ppmm): Use %. before size suffixes. (mc88110 umul_ppmm, udiv_qrnnd): Rewrite. (mc88000): Get UMUL_TIME and UDIV_TIME right. (mips): Get UMUL_TIME right. (ns32000 umul_ppmm): New definition. (ns32000 udiv_qrnnd): Rename from bogus div_qrnnd, rewrite. (powerpc umul_ppmm, smul_ppmm): New definitions. (_IBMR2/powerpc add_ssaaaa, sub_ddmmss): Improve. (pyr umul_ppmm): Fix typo. (sparc add_ssaaaa, sub_ddmmss): Match constant 0 for all inputs. (vax sdiv_qrnnd): New definition. From-SVN: r7629
This commit is contained in:
Torbjorn Granlund
parent
ab0b65811b
commit
f71c71f188
404
gcc/longlong.h
404
gcc/longlong.h
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@ -1,5 +1,5 @@
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/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
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Copyright (C) 1991, 1992 Free Software Foundation, Inc.
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Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
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This definition file is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public
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@ -72,7 +72,7 @@
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Please add support for more CPUs here, or improve the current support
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for the CPUs below!
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(E.g. WE32100, i960, IBM360.) */
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(E.g. WE32100, IBM360.) */
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#if defined (__GNUC__) && !defined (NO_ASM)
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@ -86,7 +86,7 @@
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#define __AND_CLOBBER_CC , "cc"
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#endif /* __GNUC__ < 2 */
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#if defined (__a29k__) || defined (___AM29K__)
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#if defined (__a29k__) || defined (_AM29K)
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %1,%4,%5
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addc %0,%2,%3" \
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@ -149,8 +149,57 @@
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"rI" ((USItype)(bh)), \
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"r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("; Inlined umul_ppmm
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mov r0,%2 lsr 16
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mov r2,%3 lsr 16
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bic r1,%2,r0 lsl 16
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bic r2,%3,r2 lsl 16
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mul %1,r1,r2
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mul r2,r0,r2
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mul r1,%0,r1
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mul %0,r0,%0
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adds r1,r2,r1
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addcs %0,%0,0x10000
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adds %1,%1,r1 lsl 16
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adc %0,%0,r1 lsr 16" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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: "r" ((USItype)(a)), \
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"r" ((USItype)(b)) \
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: "r0", "r1", "r2")
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#define UMUL_TIME 20
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#define UDIV_TIME 100
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#endif /* __arm__ */
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#if defined (__clipper__)
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#define umul_ppmm(w1, w0, u, v) \
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({union {UDItype __ll; \
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struct {USItype __l, __h;} __i; \
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} __xx; \
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__asm__ ("mulwux %2,%0" \
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: "=r" (__xx.__ll) \
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: "%0" ((USItype)(u)), \
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"r" ((USItype)(v))); \
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(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
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#define smul_ppmm(w1, w0, u, v) \
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({union {DItype __ll; \
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struct {SItype __l, __h;} __i; \
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} __xx; \
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__asm__ ("mulwx %2,%0" \
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: "=r" (__xx.__ll) \
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: "%0" ((SItype)(u)), \
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"r" ((SItype)(v))); \
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(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
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#define __umulsidi3(u, v) \
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({UDItype __w; \
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__asm__ ("mulwux %2,%0" \
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: "=r" (__w) \
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: "%0" ((USItype)(u)), \
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"r" ((USItype)(v))); \
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__w; })
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#endif /* __clipper__ */
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#if defined (__gmicro__)
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add.w %5,%1
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@ -229,6 +278,27 @@
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#define UMUL_TIME 30
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#endif
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#define UDIV_TIME 40
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#define count_leading_zeros(count, x) \
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do { \
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USItype __tmp; \
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__asm__ ( \
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"ldi 1,%0
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extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
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extru,tr %1,15,16,%1 ; No. Shift down, skip add.
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ldo 16(%0),%0 ; Yes. Perform add.
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extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
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extru,tr %1,23,8,%1 ; No. Shift down, skip add.
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ldo 8(%0),%0 ; Yes. Perform add.
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extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
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extru,tr %1,27,4,%1 ; No. Shift down, skip add.
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ldo 4(%0),%0 ; Yes. Perform add.
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extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
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extru,tr %1,29,2,%1 ; No. Shift down, skip add.
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ldo 2(%0),%0 ; Yes. Perform add.
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extru %1,30,1,%1 ; Extract bit 1.
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sub %0,%1,%0 ; Subtract it.
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" : "=r" (count), "=r" (__tmp) : "1" (x)); \
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} while (0)
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#endif
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#if defined (__i386__) || defined (__i486__)
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@ -315,54 +385,24 @@
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#endif
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#endif /* __i860__ */
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#if defined (___IBMR2__) /* IBM RS6000 */
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("{a%I5|add%I5c} %1,%4,%5
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{ae|adde} %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"r" ((USItype)(bh)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("{sf%I4|subf%I4c} %1,%5,%4
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{sfe|subfe} %0,%3,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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"r" ((USItype)(bh)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl)))
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#define umul_ppmm(xh, xl, m0, m1) \
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do { \
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USItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("mul %0,%2,%3" \
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: "=r" ((USItype)(xh)), \
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"=q" ((USItype)(xl)) \
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: "r" (__m0), \
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"r" (__m1)); \
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(xh) += ((((SItype) __m0 >> 31) & __m1) \
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+ (((SItype) __m1 >> 31) & __m0)); \
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} while (0)
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#define smul_ppmm(xh, xl, m0, m1) \
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__asm__ ("mul %0,%2,%3" \
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: "=r" ((USItype)(xh)), \
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"=q" ((USItype)(xl)) \
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: "r" ((USItype)(m0)), \
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"r" ((USItype)(m1)))
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#define UMUL_TIME 8
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#define sdiv_qrnnd(q, r, nh, nl, d) \
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__asm__ ("div %0,%2,%4" \
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: "=r" ((USItype)(q)), "=q" ((USItype)(r)) \
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: "r" ((USItype)(nh)), "1" ((USItype)(nl)), "r" ((USItype)(d)))
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#define UDIV_TIME 40
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#define UDIV_NEEDS_NORMALIZATION 1
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#define count_leading_zeros(count, x) \
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__asm__ ("{cntlz|cntlzw} %0,%1" \
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: "=r" ((USItype)(count)) \
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: "r" ((USItype)(x)))
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#endif /* ___IBMR2__ */
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#if defined (__i960__)
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#define umul_ppmm(w1, w0, u, v) \
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({union {UDItype __ll; \
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struct {USItype __l, __h;} __i; \
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} __xx; \
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__asm__ ("emul %2,%1,%0" \
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: "=d" (__xx.__ll) \
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: "%dI" ((USItype)(u)), \
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"dI" ((USItype)(v))); \
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(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
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#define __umulsidi3(u, v) \
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({UDItype __w; \
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__asm__ ("emul %2,%1,%0" \
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: "=d" (__w) \
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: "%dI" ((USItype)(u)), \
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"dI" ((USItype)(v))); \
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__w; })
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#endif /* __i960__ */
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#if defined (__mc68000__)
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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@ -414,31 +454,31 @@
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/* %/ inserts REGISTER_PREFIX. */
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("| Inlined umul_ppmm
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movel %2,%/d0
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movel %3,%/d1
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movel %/d0,%/d2
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move%.l %2,%/d0
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move%.l %3,%/d1
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move%.l %/d0,%/d2
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swap %/d0
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movel %/d1,%/d3
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move%.l %/d1,%/d3
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swap %/d1
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movew %/d2,%/d4
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move%.w %/d2,%/d4
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mulu %/d3,%/d4
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mulu %/d1,%/d2
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mulu %/d0,%/d3
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mulu %/d0,%/d1
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movel %/d4,%/d0
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eorw %/d0,%/d0
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move%.l %/d4,%/d0
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eor%.w %/d0,%/d0
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swap %/d0
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addl %/d0,%/d2
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addl %/d3,%/d2
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add%.l %/d0,%/d2
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add%.l %/d3,%/d2
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jcc 1f
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addl #65536,%/d1
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add%.l #65536,%/d1
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1: swap %/d2
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moveq #0,%/d0
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movew %/d2,%/d0
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movew %/d4,%/d2
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movel %/d2,%1
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addl %/d1,%/d0
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movel %/d0,%0" \
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move%.w %/d2,%/d0
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move%.w %/d4,%/d2
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move%.l %/d2,%1
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add%.l %/d1,%/d0
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move%.l %/d0,%0" \
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: "=g" ((USItype)(xh)), \
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"=g" ((USItype)(xl)) \
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: "g" ((USItype)(a)), \
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@ -468,8 +508,6 @@
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"rJ" ((USItype)(bh)), \
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"rJ" ((USItype)(al)), \
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"rJ" ((USItype)(bl)))
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#define UMUL_TIME 17
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#define UDIV_TIME 150
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#define count_leading_zeros(count, x) \
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do { \
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USItype __cbtmp; \
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@ -479,29 +517,35 @@
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(count) = __cbtmp ^ 31; \
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} while (0)
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#if defined (__mc88110__)
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("mulu.d r10,%2,%3
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or %0,r10,0
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or %1,r11,0" \
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: "=r" (w1), \
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"=r" (w0) \
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: "r" ((USItype)(u)), \
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"r" ((USItype)(v)) \
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: "r10", "r11")
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#define umul_ppmm(wh, wl, u, v) \
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do { \
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union {UDItype __ll; \
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struct {USItype __h, __l;} __i; \
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} __xx; \
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__asm__ ("mulu.d %0,%1,%2" \
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: "=r" (__xx.__ll) \
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: "r" ((USItype)(u)), \
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"r" ((USItype)(v))); \
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(wh) = __xx.__i.__h; \
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(wl) = __xx.__i.__l; \
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} while (0)
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#define udiv_qrnnd(q, r, n1, n0, d) \
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__asm__ ("or r10,%2,0
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or r11,%3,0
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divu.d r10,r10,%4
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mulu %1,%4,r11
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subu %1,%3,%1
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or %0,r11,0" \
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: "=r" (q), \
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"=&r" (r) \
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: "r" ((USItype)(n1)), \
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"r" ((USItype)(n0)), \
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"r" ((USItype)(d)) \
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: "r10", "r11")
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#endif
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({union {UDItype __ll; \
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struct {USItype __h, __l;} __i; \
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} __xx; \
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USItype __q; \
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__xx.__i.__h = (n1); __xx.__i.__l = (n0); \
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__asm__ ("divu.d %0,%1,%2" \
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: "=r" (__q) \
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: "r" (__xx.__ll), \
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"r" ((USItype)(d))); \
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(r) = (n0) - __q * (d); (q) = __q; })
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#define UMUL_TIME 5
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#define UDIV_TIME 25
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#else
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#define UMUL_TIME 17
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#define UDIV_TIME 150
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#endif /* __mc88110__ */
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#endif /* __m88000__ */
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#if defined (__mips__)
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@ -513,11 +557,20 @@
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"=d" ((USItype)(w1)) \
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: "d" ((USItype)(u)), \
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"d" ((USItype)(v)))
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#define UMUL_TIME 5
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#define UMUL_TIME 10
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#define UDIV_TIME 100
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#endif /* __mips__ */
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#if defined (__ns32000__)
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#define umul_ppmm(w1, w0, u, v) \
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({union {UDItype __ll; \
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struct {USItype __l, __h;} __i; \
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} __xx; \
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__asm__ ("meid %2,%0" \
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: "=g" (__xx.__ll) \
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: "%0" ((USItype)(u)), \
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"g" ((USItype)(v))); \
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(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
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#define __umulsidi3(u, v) \
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({UDItype __w; \
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__asm__ ("meid %2,%0" \
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@ -525,20 +578,137 @@
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: "%0" ((USItype)(u)), \
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"g" ((USItype)(v))); \
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__w; })
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#define div_qrnnd(q, r, n1, n0, d) \
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__asm__ ("movd %2,r0
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movd %3,r1
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deid %4,r0
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movd r1,%0
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movd r0,%1" \
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: "=g" ((USItype)(q)), \
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"=g" ((USItype)(r)) \
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: "g" ((USItype)(n0)), \
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"g" ((USItype)(n1)), \
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"g" ((USItype)(d)) \
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: "r0", "r1")
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#define udiv_qrnnd(q, r, n1, n0, d) \
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({union {UDItype __ll; \
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struct {USItype __l, __h;} __i; \
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} __xx; \
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__xx.__i.__h = (n1); __xx.__i.__l = (n0); \
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__asm__ ("deid %2,%0" \
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: "=g" (__xx.__ll) \
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: "0" (__xx.__ll), \
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"g" ((USItype)(d))); \
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(r) = __xx.__i.__l; (q) = __xx.__i.__h; })
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#endif /* __ns32000__ */
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#if (defined (__powerpc__) || defined (___IBMR2__)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (bh) && (bh) == 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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else \
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__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"r" ((USItype)(bh)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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} while (0)
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (ah) && (ah) == 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(bh)), \
|
||||
"rI" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl))); \
|
||||
else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(bh)), \
|
||||
"rI" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl))); \
|
||||
else if (__builtin_constant_p (bh) && (bh) == 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(ah)), \
|
||||
"rI" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl))); \
|
||||
else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(ah)), \
|
||||
"rI" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl))); \
|
||||
else \
|
||||
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(ah)), \
|
||||
"r" ((USItype)(bh)), \
|
||||
"rI" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl))); \
|
||||
} while (0)
|
||||
#define count_leading_zeros(count, x) \
|
||||
__asm__ ("{cntlz|cntlzw} %0,%1" \
|
||||
: "=r" ((USItype)(count)) \
|
||||
: "r" ((USItype)(x)))
|
||||
#if defined (__powerpc__)
|
||||
#define umul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
USItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhwu %0,%1,%2" \
|
||||
: "=r" ((USItype) ph) \
|
||||
: "%r" (__m0), \
|
||||
"r" (__m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define UMUL_TIME 15
|
||||
#define smul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
SItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhw %0,%1,%2" \
|
||||
: "=r" ((SItype) ph) \
|
||||
: "%r" (__m0), \
|
||||
"r" (__m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define SMUL_TIME 14
|
||||
#define UDIV_TIME 120
|
||||
#else
|
||||
#define umul_ppmm(xh, xl, m0, m1) \
|
||||
do { \
|
||||
USItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mul %0,%2,%3" \
|
||||
: "=r" ((USItype)(xh)), \
|
||||
"=q" ((USItype)(xl)) \
|
||||
: "r" (__m0), \
|
||||
"r" (__m1)); \
|
||||
(xh) += ((((SItype) __m0 >> 31) & __m1) \
|
||||
+ (((SItype) __m1 >> 31) & __m0)); \
|
||||
} while (0)
|
||||
#define UMUL_TIME 8
|
||||
#define smul_ppmm(xh, xl, m0, m1) \
|
||||
__asm__ ("mul %0,%2,%3" \
|
||||
: "=r" ((SItype)(xh)), \
|
||||
"=q" ((SItype)(xl)) \
|
||||
: "r" (m0), \
|
||||
"r" (m1))
|
||||
#define SMUL_TIME 4
|
||||
#define sdiv_qrnnd(q, r, nh, nl, d) \
|
||||
__asm__ ("div %0,%2,%4" \
|
||||
: "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
|
||||
: "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
|
||||
#define UDIV_TIME 100
|
||||
#endif
|
||||
#endif /* Power architecture variants. */
|
||||
|
||||
#if defined (__pyr__)
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addw %5,%1
|
||||
|
|
@ -569,7 +739,7 @@
|
|||
: "=r" (__xx.__i.__h), \
|
||||
"=r" (__xx.__i.__l) \
|
||||
: "1" (__xx.__i.__l), \
|
||||
"g" ((UDItype)(v))); \
|
||||
"g" ((USItype)(v))); \
|
||||
(w1) = __xx.__i.__h; \
|
||||
(w0) = __xx.__i.__l;})
|
||||
#endif /* __pyr__ */
|
||||
|
|
@ -645,23 +815,23 @@
|
|||
|
||||
#if defined (__sparc__)
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addcc %4,%5,%1
|
||||
addx %2,%3,%0" \
|
||||
__asm__ ("addcc %r4,%5,%1
|
||||
addx %r2,%3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%r" ((USItype)(ah)), \
|
||||
: "%rJ" ((USItype)(ah)), \
|
||||
"rI" ((USItype)(bh)), \
|
||||
"%r" ((USItype)(al)), \
|
||||
"%rJ" ((USItype)(al)), \
|
||||
"rI" ((USItype)(bl)) \
|
||||
__CLOBBER_CC)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subcc %4,%5,%1
|
||||
subx %2,%3,%0" \
|
||||
__asm__ ("subcc %r4,%5,%1
|
||||
subx %r2,%3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "r" ((USItype)(ah)), \
|
||||
: "rJ" ((USItype)(ah)), \
|
||||
"rI" ((USItype)(bh)), \
|
||||
"r" ((USItype)(al)), \
|
||||
"rJ" ((USItype)(al)), \
|
||||
"rI" ((USItype)(bl)) \
|
||||
__CLOBBER_CC)
|
||||
#if defined (__sparc_v8__)
|
||||
|
|
@ -861,6 +1031,16 @@
|
|||
(xh) += ((((SItype) __m0 >> 31) & __m1) \
|
||||
+ (((SItype) __m1 >> 31) & __m0)); \
|
||||
} while (0)
|
||||
#define sdiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { \
|
||||
union {DItype __ll; \
|
||||
struct {SItype __l, __h;} __i; \
|
||||
} __xx; \
|
||||
__xx.__i.__h = n1; __xx.__i.__l = n0; \
|
||||
__asm__ ("ediv %3,%2,%0,%1" \
|
||||
: "=g" (q), "=g" (r) \
|
||||
: "g" (__n1n0.ll), "g" (d)); \
|
||||
} while (0)
|
||||
#endif /* __vax__ */
|
||||
|
||||
#endif /* __GNUC__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue