[AArch64] Add "FULL" to SVE mode iterator names
An upcoming patch will make more use of partial/unpacked SVE vectors. We then need a distinction between mode iterators that include partial modes and those that only include "full" modes. This patch prepares for that by adding "FULL" to the names of iterators that only select full modes. There should be no change in behaviour. 2019-11-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SVE_ALL): Rename to... (SVE_FULL): ...this. (SVE_I): Rename to... (SVE_FULL_I): ...this. (SVE_F): Rename to... (SVE_FULL_F): ...this. (SVE_BHSI): Rename to... (SVE_FULL_BHSI): ...this. (SVE_HSD): Rename to... (SVE_FULL_HSD): ...this. (SVE_HSDI): Rename to... (SVE_FULL_HSDI): ...this. (SVE_HSF): Rename to... (SVE_FULL_HSF): ...this. (SVE_SD): Rename to... (SVE_FULL_SD): ...this. (SVE_SDI): Rename to... (SVE_FULL_SDI): ...this. (SVE_SDF): Rename to... (SVE_FULL_SDF): ...this. (SVE_S): Rename to... (SVE_FULL_S): ...this. (SVE_D): Rename to... (SVE_FULL_D): ...this. * config/aarch64/aarch64-sve.md: Apply the above renaming throughout. * config/aarch64/aarch64-sve2.md: Likewise. From-SVN: r278338
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
eb23241ba8
commit
f75cdd2c4e
@ -1,3 +1,32 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_ALL): Rename to...
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(SVE_FULL): ...this.
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(SVE_I): Rename to...
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(SVE_FULL_I): ...this.
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(SVE_F): Rename to...
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(SVE_FULL_F): ...this.
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(SVE_BHSI): Rename to...
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(SVE_FULL_BHSI): ...this.
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(SVE_HSD): Rename to...
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(SVE_FULL_HSD): ...this.
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(SVE_HSDI): Rename to...
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(SVE_FULL_HSDI): ...this.
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(SVE_HSF): Rename to...
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(SVE_FULL_HSF): ...this.
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(SVE_SD): Rename to...
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(SVE_FULL_SD): ...this.
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(SVE_SDI): Rename to...
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(SVE_FULL_SDI): ...this.
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(SVE_SDF): Rename to...
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(SVE_FULL_SDF): ...this.
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(SVE_S): Rename to...
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(SVE_FULL_S): ...this.
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(SVE_D): Rename to...
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(SVE_FULL_D): ...this.
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* config/aarch64/aarch64-sve.md: Apply the above renaming throughout.
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* config/aarch64/aarch64-sve2.md: Likewise.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.opt (--param=aarch64-sve-compare-costs):
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File diff suppressed because it is too large
Load Diff
@ -20,12 +20,13 @@
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;; Integer average (floor).
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(define_expand "<u>avg<mode>3_floor"
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(unspec:SVE_FULL_I
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[(match_dup 3)
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(unspec:SVE_I [(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "register_operand")]
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HADD)]
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(unspec:SVE_FULL_I
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[(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "register_operand")]
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HADD)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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{
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@ -35,12 +36,13 @@
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;; Integer average (rounding).
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(define_expand "<u>avg<mode>3_ceil"
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(unspec:SVE_FULL_I
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[(match_dup 3)
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(unspec:SVE_I [(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "register_operand")]
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RHADD)]
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(unspec:SVE_FULL_I
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[(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "register_operand")]
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RHADD)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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{
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@ -50,12 +52,13 @@
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;; Predicated halving addsub.
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(define_insn "*<sur>h<addsub><mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(unspec:SVE_I [(match_operand:SVE_I 2 "register_operand" "%0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w")]
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HADDSUB)]
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(unspec:SVE_FULL_I
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[(match_operand:SVE_FULL_I 2 "register_operand" "%0, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w")]
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HADDSUB)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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"@
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@ -67,17 +70,18 @@
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;; Multiply long top / bottom.
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(define_insn "<su>mull<bt><Vwide>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(unspec:<VWIDE> [(match_operand:SVE_BHSI 1 "register_operand" "w")
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(match_operand:SVE_BHSI 2 "register_operand" "w")]
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MULLBT))]
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(unspec:<VWIDE>
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "w")
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(match_operand:SVE_FULL_BHSI 2 "register_operand" "w")]
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MULLBT))]
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"TARGET_SVE2"
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"<su>mull<bt>\t%0.<Vewtype>, %1.<Vetype>, %2.<Vetype>"
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)
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;; (Rounding) Right shift narrow bottom.
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(define_insn "<r>shrnb<mode>"
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[(set (match_operand:SVE_BHSI 0 "register_operand" "=w")
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(unspec:SVE_BHSI
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:<VWIDE> 1 "register_operand" "w")
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(match_operand 2 "aarch64_simd_shift_imm_offset_<Vel>" "")]
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SHRNB))]
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@ -87,9 +91,9 @@
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;; (Rounding) Right shift narrow top.
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(define_insn "<r>shrnt<mode>"
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[(set (match_operand:SVE_BHSI 0 "register_operand" "=w")
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(unspec:SVE_BHSI
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[(match_operand:SVE_BHSI 1 "register_operand" "0")
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "0")
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(match_operand:<VWIDE> 2 "register_operand" "w")
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(match_operand 3 "aarch64_simd_shift_imm_offset_<Vel>" "i")]
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SHRNT))]
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@ -99,12 +103,13 @@
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;; Unpredicated integer multiply-high-with-(round-and-)scale.
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(define_expand "<su>mulh<r>s<mode>3"
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[(set (match_operand:SVE_BHSI 0 "register_operand")
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(unspec:SVE_BHSI
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand")
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(unspec:SVE_FULL_BHSI
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[(match_dup 3)
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(unspec:SVE_BHSI [(match_operand:SVE_BHSI 1 "register_operand")
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(match_operand:SVE_BHSI 2 "register_operand")]
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MULHRS)]
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand")
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(match_operand:SVE_FULL_BHSI 2 "register_operand")]
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MULHRS)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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{
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@ -125,15 +130,15 @@
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;; Unpredicated signed / unsigned shift-right accumulate.
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(define_insn_and_rewrite "*aarch64_sve2_sra<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(plus:SVE_I
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w")
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(plus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(SHIFTRT:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w")
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(match_operand:SVE_I 3 "aarch64_simd_rshift_imm" "Dr"))]
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(SHIFTRT:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w")
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(match_operand:SVE_FULL_I 3 "aarch64_simd_rshift_imm" "Dr"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_I 1 "register_operand" "0")))]
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(match_operand:SVE_FULL_I 1 "register_operand" "0")))]
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"TARGET_SVE2"
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"<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3"
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"&& !CONSTANT_P (operands[4])"
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@ -144,12 +149,12 @@
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;; Unpredicated 3-way exclusive OR.
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(define_insn "*aarch64_sve2_eor3<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, ?&w")
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(xor:SVE_I
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(xor:SVE_I
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(match_operand:SVE_I 1 "register_operand" "0, w, w, w")
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(match_operand:SVE_I 2 "register_operand" "w, 0, w, w"))
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(match_operand:SVE_I 3 "register_operand" "w, w, 0, w")))]
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, w, ?&w")
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(xor:SVE_FULL_I
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(xor:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "0, w, w, w")
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(match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w, w"))
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w, 0, w")))]
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"TARGET_SVE2"
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"@
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eor3\t%0.d, %0.d, %2.d, %3.d
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@ -161,14 +166,14 @@
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;; Use NBSL for vector NOR.
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(define_insn_and_rewrite "*aarch64_sve2_nor<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand 3)
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(and:SVE_I
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(not:SVE_I
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(match_operand:SVE_I 1 "register_operand" "%0, w"))
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(not:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w")))]
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(and:SVE_FULL_I
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "%0, w"))
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, w")))]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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"@
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@ -183,14 +188,14 @@
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;; Use NBSL for vector NAND.
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(define_insn_and_rewrite "*aarch64_sve2_nand<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand 3)
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(ior:SVE_I
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(not:SVE_I
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(match_operand:SVE_I 1 "register_operand" "%0, w"))
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(not:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w")))]
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(ior:SVE_FULL_I
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "%0, w"))
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, w")))]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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"@
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@ -206,13 +211,13 @@
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;; Unpredicated bitwise select.
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;; (op3 ? bsl_mov : bsl_dup) == (((bsl_mov ^ bsl_dup) & op3) ^ bsl_dup)
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(define_insn "*aarch64_sve2_bsl<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(xor:SVE_I
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(and:SVE_I
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(xor:SVE_I
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(match_operand:SVE_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_I 2 "register_operand" "<bsl_2nd>, w"))
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(xor:SVE_FULL_I
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(and:SVE_FULL_I
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(xor:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_FULL_I 2 "register_operand" "<bsl_2nd>, w"))
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_dup BSL_DUP)))]
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"TARGET_SVE2"
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"@
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@ -224,16 +229,16 @@
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;; Unpredicated bitwise inverted select.
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;; (~(op3 ? bsl_mov : bsl_dup)) == (~(((bsl_mov ^ bsl_dup) & op3) ^ bsl_dup))
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(define_insn_and_rewrite "*aarch64_sve2_nbsl<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(not:SVE_I
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(xor:SVE_I
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(and:SVE_I
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(xor:SVE_I
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(match_operand:SVE_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_I 2 "register_operand" "<bsl_2nd>, w"))
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(not:SVE_FULL_I
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(xor:SVE_FULL_I
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(and:SVE_FULL_I
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(xor:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_FULL_I 2 "register_operand" "<bsl_2nd>, w"))
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_dup BSL_DUP)))]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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@ -250,17 +255,17 @@
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;; Unpredicated bitwise select with inverted first operand.
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;; (op3 ? ~bsl_mov : bsl_dup) == ((~(bsl_mov ^ bsl_dup) & op3) ^ bsl_dup)
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(define_insn_and_rewrite "*aarch64_sve2_bsl1n<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(xor:SVE_I
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(and:SVE_I
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(xor:SVE_FULL_I
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(and:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(not:SVE_I
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(xor:SVE_I
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(match_operand:SVE_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_I 2 "register_operand" "<bsl_2nd>, w")))]
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(not:SVE_FULL_I
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(xor:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_FULL_I 2 "register_operand" "<bsl_2nd>, w")))]
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UNSPEC_PRED_X)
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_dup BSL_DUP)))]
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"TARGET_SVE2"
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"@
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@ -276,17 +281,17 @@
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;; Unpredicated bitwise select with inverted second operand.
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;; (bsl_dup ? bsl_mov : ~op3) == ((bsl_dup & bsl_mov) | (~op3 & ~bsl_dup))
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(define_insn_and_rewrite "*aarch64_sve2_bsl2n<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(ior:SVE_I
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(and:SVE_I
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(match_operand:SVE_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_I 2 "register_operand" "<bsl_2nd>, w"))
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(unspec:SVE_I
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(ior:SVE_FULL_I
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(and:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "<bsl_1st>, w")
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(match_operand:SVE_FULL_I 2 "register_operand" "<bsl_2nd>, w"))
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(and:SVE_I
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(not:SVE_I
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(not:SVE_I
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(and:SVE_FULL_I
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(not:SVE_FULL_I
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(not:SVE_FULL_I
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(match_dup BSL_DUP)))]
|
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UNSPEC_PRED_X)))]
|
||||
"TARGET_SVE2"
|
||||
@ -303,18 +308,18 @@
|
||||
;; Unpredicated bitwise select with inverted second operand, alternative form.
|
||||
;; (bsl_dup ? bsl_mov : ~op3) == ((bsl_dup & bsl_mov) | (~bsl_dup & ~op3))
|
||||
(define_insn_and_rewrite "*aarch64_sve2_bsl2n<mode>"
|
||||
[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
|
||||
(ior:SVE_I
|
||||
(and:SVE_I
|
||||
(match_operand:SVE_I 1 "register_operand" "<bsl_1st>, w")
|
||||
(match_operand:SVE_I 2 "register_operand" "<bsl_2nd>, w"))
|
||||
(unspec:SVE_I
|
||||
[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
|
||||
(ior:SVE_FULL_I
|
||||
(and:SVE_FULL_I
|
||||
(match_operand:SVE_FULL_I 1 "register_operand" "<bsl_1st>, w")
|
||||
(match_operand:SVE_FULL_I 2 "register_operand" "<bsl_2nd>, w"))
|
||||
(unspec:SVE_FULL_I
|
||||
[(match_operand 4)
|
||||
(and:SVE_I
|
||||
(not:SVE_I
|
||||
(and:SVE_FULL_I
|
||||
(not:SVE_FULL_I
|
||||
(match_dup BSL_DUP))
|
||||
(not:SVE_I
|
||||
(match_operand:SVE_I 3 "register_operand" "w, w")))]
|
||||
(not:SVE_FULL_I
|
||||
(match_operand:SVE_FULL_I 3 "register_operand" "w, w")))]
|
||||
UNSPEC_PRED_X)))]
|
||||
"TARGET_SVE2"
|
||||
"@
|
||||
|
||||
@ -284,10 +284,6 @@
|
||||
;; count.
|
||||
(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
|
||||
|
||||
;; All SVE vector modes.
|
||||
(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
|
||||
VNx8HF VNx4SF VNx2DF])
|
||||
|
||||
;; Iterators for single modes, for "@" patterns.
|
||||
(define_mode_iterator VNx8HI_ONLY [VNx8HI])
|
||||
(define_mode_iterator VNx4SI_ONLY [VNx4SI])
|
||||
@ -302,38 +298,46 @@
|
||||
VNx64QI VNx32HI VNx16SI VNx8DI
|
||||
VNx32HF VNx16SF VNx8DF])
|
||||
|
||||
;; SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
|
||||
(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
|
||||
;; All fully-packed SVE vector modes.
|
||||
(define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI
|
||||
VNx8HF VNx4SF VNx2DF])
|
||||
|
||||
;; SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_HSDI [VNx8HI VNx4SI VNx2DI])
|
||||
;; All fully-packed SVE integer vector modes.
|
||||
(define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI])
|
||||
|
||||
;; SVE floating-point vector modes that have 16-bit or 32-bit elements.
|
||||
(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
|
||||
;; All fully-packed SVE floating-point vector modes.
|
||||
(define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
|
||||
|
||||
;; SVE integer vector modes that have 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
|
||||
;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
|
||||
;; elements.
|
||||
(define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
|
||||
|
||||
;; SVE floating-point vector modes that have 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_SDF [VNx4SF VNx2DF])
|
||||
;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
|
||||
|
||||
;; All SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
|
||||
;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit
|
||||
;; elements.
|
||||
(define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI])
|
||||
|
||||
;; All SVE vector modes that have 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
|
||||
;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit
|
||||
;; elements.
|
||||
(define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF])
|
||||
|
||||
;; All SVE vector modes that have 32-bit elements.
|
||||
(define_mode_iterator SVE_S [VNx4SI VNx4SF])
|
||||
;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
|
||||
|
||||
;; All SVE vector modes that have 64-bit elements.
|
||||
(define_mode_iterator SVE_D [VNx2DI VNx2DF])
|
||||
;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements.
|
||||
(define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI])
|
||||
|
||||
;; All SVE integer vector modes.
|
||||
(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
|
||||
;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
|
||||
;; elements.
|
||||
(define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
|
||||
|
||||
;; All SVE floating-point vector modes.
|
||||
(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
|
||||
;; Fully-packed SVE vector modes that have 32-bit elements.
|
||||
(define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF])
|
||||
|
||||
;; Fully-packed SVE vector modes that have 64-bit elements.
|
||||
(define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF])
|
||||
|
||||
;; All partial SVE modes.
|
||||
(define_mode_iterator SVE_PARTIAL [VNx2QI
|
||||
|
||||
Loading…
Reference in New Issue
Block a user