[ARC] Add/update combiner patterns.
gcc/ 2018-01-26 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (add_shift): New pattern. (add_shift2): Likewise. (sub_shift): Likewise. (sub_shift_cmp0_noout): Likewise. (compare_si_ashiftsi): Likewise. (xbfu_cmp0_noout): New combine pattern. (xbfu_cmp0"): Likewise. (movsi_set_cc_insn): Place the predicable variant first. (commutative_binary_cmp0_noout): Remove clobber. (commutative_binary_cmp0): New pattern. (noncommutative_binary_cmp0): Likewise. (noncommutative_binary_cmp0_noout): Likewise. (noncommutative_binary_comparison_result_used): Removed. (rsub_cmp0): New pattern. (rsub_cmp0_noout): Likewise. (extzvsi): Changed, keep only meaningful variants. (SQH, SEZ): New iterators. (SQH_postfix): New mode attribute. (SEZ_prefix): New code attribute. (<SEZ_prefix>xt<SQH_postfix>_cmp0_noout): New instruction pattern. (<SEZ_prefix>xt<SQH_postfix>_cmp0): Likewise. * config/arc/predicates.md (cc_set_register): Use CC_REG instead of numerical value. (noncommutative_operator): Check the availability of barrel shifter option. From-SVN: r259237
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
46e58e180d
commit
f7ace5d5c2
@ -1,3 +1,31 @@
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2018-04-09 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.md (add_shift): New pattern.
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(add_shift2): Likewise.
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(sub_shift): Likewise.
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(sub_shift_cmp0_noout): Likewise.
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(compare_si_ashiftsi): Likewise.
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(xbfu_cmp0_noout): New combine pattern.
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(xbfu_cmp0"): Likewise.
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(movsi_set_cc_insn): Place the predicable variant first.
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(commutative_binary_cmp0_noout): Remove clobber.
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(commutative_binary_cmp0): New pattern.
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(noncommutative_binary_cmp0): Likewise.
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(noncommutative_binary_cmp0_noout): Likewise.
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(noncommutative_binary_comparison_result_used): Removed.
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(rsub_cmp0): New pattern.
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(rsub_cmp0_noout): Likewise.
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(extzvsi): Changed, keep only meaningful variants.
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(SQH, SEZ): New iterators.
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(SQH_postfix): New mode attribute.
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(SEZ_prefix): New code attribute.
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(<SEZ_prefix>xt<SQH_postfix>_cmp0_noout): New instruction pattern.
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(<SEZ_prefix>xt<SQH_postfix>_cmp0): Likewise.
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* config/arc/predicates.md (cc_set_register): Use CC_REG instead
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of numerical value.
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(noncommutative_operator): Check the availability of barrel
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shifter option.
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2018-04-09 Richard Biener <rguenther@suse.de>
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PR tree-optimization/85284
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@ -794,20 +794,90 @@
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"st%U0 %1,%0\;st%U0.di %1,%0"
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[(set_attr "type" "store")])
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;; Combiner patterns for compare with zero
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(define_mode_iterator SQH [QI HI])
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(define_mode_attr SQH_postfix [(QI "b") (HI "%_")])
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(define_code_iterator SEZ [sign_extend zero_extend])
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(define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")])
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(define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r"))
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(const_int 0)))]
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""
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"<SEZ_prefix><SQH_postfix>.f\\t0,%1"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")])
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(define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0"
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[(set (match_operand 0 "cc_set_register" "")
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(compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 2 "register_operand" "=r")
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(SEZ:SI (match_dup 1)))]
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""
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"<SEZ_prefix><SQH_postfix>.f\\t%2,%1"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")])
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(define_insn "*xbfu_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(compare:CC_Z
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(zero_extract:SI
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(match_operand:SI 1 "register_operand" " r,r")
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(match_operand:SI 2 "const_int_operand" "C3p,n")
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(match_operand:SI 3 "const_int_operand" " n,n"))
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(const_int 0)))]
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"TARGET_HS && TARGET_BARREL_SHIFTER"
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{
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int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
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operands[2] = GEN_INT (assemble_op2);
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return "xbfu%?.f\\t0,%1,%2";
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}
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[(set_attr "type" "shift")
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(set_attr "iscompact" "false")
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(set_attr "length" "4,8")
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(set_attr "predicable" "no")
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(set_attr "cond" "set_zn")])
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(define_insn "*xbfu_cmp0"
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[(set (match_operand 4 "cc_set_register" "")
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(compare:CC_Z
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(zero_extract:SI
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(match_operand:SI 1 "register_operand" "0 ,r,0")
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(match_operand:SI 2 "const_int_operand" "C3p,n,n")
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(match_operand:SI 3 "const_int_operand" "n ,n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
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"TARGET_HS && TARGET_BARREL_SHIFTER"
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{
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int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
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operands[2] = GEN_INT (assemble_op2);
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return "xbfu%?.f\\t%0,%1,%2";
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}
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[(set_attr "type" "shift")
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(set_attr "iscompact" "false")
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(set_attr "length" "4,8,8")
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(set_attr "predicable" "yes,no,yes")
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(set_attr "cond" "set_zn")])
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; splitting to 'tst' allows short insns and combination into brcc.
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(define_insn_and_split "*movsi_set_cc_insn"
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[(set (match_operand:CC_ZN 2 "cc_set_register" "")
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(match_operator:CC_ZN 3 "zn_compare_operator"
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[(match_operand:SI 1 "nonmemory_operand" "cI,cL,Cal") (const_int 0)]))
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(set (match_operand:SI 0 "register_operand" "=w,w,w")
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[(set (match_operand 2 "cc_set_register" "")
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(match_operator 3 "zn_compare_operator"
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[(match_operand:SI 1 "nonmemory_operand" "rL,rI,Cal")
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(const_int 0)]))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(match_dup 1))]
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""
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"mov%?.f %0,%1"
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; splitting to 'tst' allows short insns and combination into brcc.
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"mov%?.f\\t%0,%1"
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"reload_completed && operands_match_p (operands[0], operands[1])"
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[(set (match_dup 2) (match_dup 3))]
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""
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[(set_attr "type" "compare")
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(set_attr "predicable" "no,yes,yes")
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(set_attr "predicable" "yes,no,yes")
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(set_attr "cond" "set_zn")
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(set_attr "length" "4,4,8")])
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@ -957,20 +1027,36 @@
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(set_attr "cond" "set_zn")
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(set_attr "length" "*,4,4,4,8")])
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(define_insn "*commutative_binary_comparison"
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[(set (match_operand:CC_ZN 0 "cc_set_register" "")
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(match_operator:CC_ZN 5 "zn_compare_operator"
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[(match_operator:SI 4 "commutative_operator"
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[(match_operand:SI 1 "register_operand" "%c,c")
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(match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
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(const_int 0)]))
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(clobber (match_scratch:SI 3 "=X,X"))]
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;; The next two patterns are for plos, ior, xor, and, and mult.
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(define_insn "*commutative_binary_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(match_operator 4 "zn_compare_operator"
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[(match_operator:SI 3 "commutative_operator"
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[(match_operand:SI 1 "register_operand" "%r,r")
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(match_operand:SI 2 "nonmemory_operand" "rL,Cal")])
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(const_int 0)]))]
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""
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"%O4.f 0,%1,%2"
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"%O3.f\\t0,%1,%2"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "length" "4,8")])
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(define_insn "*commutative_binary_cmp0"
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[(set (match_operand 3 "cc_set_register" "")
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(match_operator 5 "zn_compare_operator"
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[(match_operator:SI 4 "commutative_operator"
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[(match_operand:SI 1 "register_operand" "%0, 0,r,r")
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(match_operand:SI 2 "nonmemory_operand" "rL,rI,r,Cal")])
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(const_int 0)]))
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(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
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(match_dup 4))]
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""
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"%O4.f\\t%0,%1,%2"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "predicable" "yes,yes,no,no")
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(set_attr "length" "4,4,4,8")])
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; for flag setting 'add' instructions like if (a+b) { ...}
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; the combiner needs this pattern
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(define_insn "*addsi_compare"
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@ -1043,32 +1129,60 @@
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(set_attr "cond" "set_zn,set_zn,set_zn")
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(set_attr "length" "4,4,8")])
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; this pattern is needed by combiner for cases like if (c=a<<b) { ... }
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(define_insn "*noncommutative_binary_comparison_result_used"
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[(set (match_operand 3 "cc_register" "")
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(define_insn "*noncommutative_binary_cmp0"
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[(set (match_operand 3 "cc_set_register" "")
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(match_operator 5 "zn_compare_operator"
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[(match_operator:SI 4 "noncommutative_operator"
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[(match_operand:SI 1 "register_operand" "c,0,c")
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(match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")])
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(const_int 0)]))
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(set (match_operand:SI 0 "register_operand" "=w,w,w")
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(match_dup 4 ))]
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"TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS"
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"%O4.f %0,%1,%2"
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[(set_attr "type" "compare,compare,compare")
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(set_attr "cond" "set_zn,set_zn,set_zn")
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(set_attr "length" "4,4,8")])
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(define_insn "*noncommutative_binary_comparison"
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[(set (match_operand:CC_ZN 0 "cc_set_register" "")
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(match_operator:CC_ZN 5 "zn_compare_operator"
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[(match_operator:SI 4 "noncommutative_operator"
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[(match_operand:SI 1 "register_operand" "c,c")
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(match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
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[(match_operand:SI 1 "register_operand" "0,r,0, 0,r")
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(match_operand:SI 2 "nonmemory_operand" "rL,r,I,Cal,Cal")])
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(const_int 0)]))
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(clobber (match_scratch:SI 3 "=X,X"))]
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"TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS"
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"%O4.f 0,%1,%2"
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(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
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(match_dup 4))]
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""
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"%O4%?.f\\t%0,%1,%2"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "predicable" "yes,no,no,yes,no")
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(set_attr "length" "4,4,4,8,8")])
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(define_insn "*noncommutative_binary_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(match_operator 3 "zn_compare_operator"
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[(match_operator:SI 4 "noncommutative_operator"
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[(match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "nonmemory_operand" "rL,Cal")])
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(const_int 0)]))]
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""
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"%O4.f\\t0,%1,%2"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "length" "4,8")])
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;;rsub variants
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(define_insn "*rsub_cmp0"
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[(set (match_operand 4 "cc_set_register" "")
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(match_operator 3 "zn_compare_operator"
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[(minus:SI
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(match_operand:SI 1 "nonmemory_operand" "rL,Cal")
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(match_operand:SI 2 "register_operand" "r,r"))
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(const_int 0)]))
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(set (match_operand:SI 0 "register_operand" "=r,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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""
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"rsub.f\\t%0,%2,%1"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "length" "4,8")])
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(define_insn "*rsub_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(match_operator 3 "zn_compare_operator"
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[(minus:SI
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(match_operand:SI 1 "nonmemory_operand" "rL,Cal")
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(match_operand:SI 2 "register_operand" "r,r"))
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(const_int 0)]))]
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""
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"rsub.f\\t0,%2,%1"
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[(set_attr "type" "compare")
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(set_attr "cond" "set_zn")
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(set_attr "length" "4,8")])
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@ -5608,23 +5722,22 @@
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DONE;
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})
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(define_insn "extzvsi"
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[(set (match_operand:SI 0 "register_operand" "=r , r , r, r, r")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r , 0, 0, r")
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(match_operand:SI 2 "const_int_operand" "C3p, C3p, i, i, i")
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(match_operand:SI 3 "const_int_operand" "i , i , i, i, i")))]
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[(set (match_operand:SI 0 "register_operand" "=r , r,r,r")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "0 , r,r,0")
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(match_operand:SI 2 "const_int_operand" "C3p,C3p,n,n")
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(match_operand:SI 3 "const_int_operand" "n , n,n,n")))]
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"TARGET_HS && TARGET_BARREL_SHIFTER"
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{
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int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f);
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operands[2] = GEN_INT (assemble_op2);
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return "xbfu%? %0,%1,%2";
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return "xbfu%?\\t%0,%1,%2";
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}
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[(set_attr "type" "shift")
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(set_attr "iscompact" "false")
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(set_attr "length" "4,4,4,8,8")
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(set_attr "predicable" "yes,no,no,yes,no")
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(set_attr "cond" "canuse,nocond,nocond,canuse,nocond")])
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(set_attr "length" "4,4,8,8")
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(set_attr "predicable" "yes,no,no,yes")
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(set_attr "cond" "canuse,nocond,nocond,canuse_limm")])
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(define_insn "kflag"
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[(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")]
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@ -6423,6 +6536,77 @@
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(set_attr "type" "block")]
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)
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(define_insn "*add_shift"
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[(set (match_operand:SI 0 "register_operand" "=q,r,r")
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(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r")
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(match_operand:SI 2 "_1_2_3_operand" ""))
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(match_operand:SI 3 "nonmemory_operand" "0,r,Cal")))]
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""
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"add%2%?\\t%0,%3,%1"
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[(set_attr "length" "*,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "iscompact" "maybe,false,false")
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(set_attr "cond" "canuse,nocond,nocond")])
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(define_insn "*add_shift2"
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[(set (match_operand:SI 0 "register_operand" "=q,r,r")
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(plus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
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(ashift:SI (match_operand:SI 2 "register_operand" "q,r,r")
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(match_operand:SI 3 "_1_2_3_operand" ""))))]
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""
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"add%3%?\\t%0,%1,%2"
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[(set_attr "length" "*,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "iscompact" "maybe,false,false")
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(set_attr "cond" "canuse,nocond,nocond")])
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(define_insn "*sub_shift"
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[(set (match_operand:SI 0"register_operand" "=r,r,r")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
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(ashift:SI (match_operand:SI 2 "register_operand" "r,r,r")
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(match_operand:SI 3 "_1_2_3_operand" ""))))]
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""
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"sub%3\\t%0,%1,%2"
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[(set_attr "length" "4,4,8")
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(set_attr "cond" "canuse,nocond,nocond")
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(set_attr "predicable" "yes,no,no")])
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(define_insn "*sub_shift_cmp0_noout"
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[(set (match_operand 0 "cc_set_register" "")
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(compare:CC
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(minus:SI (match_operand:SI 1 "register_operand" "r")
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(ashift:SI (match_operand:SI 2 "register_operand" "r")
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(match_operand:SI 3 "_1_2_3_operand" "")))
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(const_int 0)))]
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""
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"sub%3.f\\t0,%1,%2"
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[(set_attr "length" "4")])
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(define_insn "*compare_si_ashiftsi"
|
||||
[(set (match_operand 0 "cc_set_register" "")
|
||||
(compare:CC (match_operand:SI 1 "register_operand" "r")
|
||||
(ashift:SI (match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "_1_2_3_operand" ""))))]
|
||||
""
|
||||
"sub%3.f\\t0,%1,%2"
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
;; Convert the sequence
|
||||
;; asl rd,rn,_1_2_3
|
||||
;; cmp ra,rd
|
||||
;; into
|
||||
;; sub{123}.f 0,ra,rn
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(ashift:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "_1_2_3_operand" "")))
|
||||
(set (reg:CC CC_REG)
|
||||
(compare:CC (match_operand:SI 3 "register_operand" "")
|
||||
(match_dup 0)))]
|
||||
"peep2_reg_dead_p (2, operands[0])"
|
||||
[(set (reg:CC CC_REG) (compare:CC (match_dup 3)
|
||||
(ashift:SI (match_dup 1) (match_dup 2))))])
|
||||
|
||||
;; include the arc-FPX instructions
|
||||
(include "fpx.md")
|
||||
|
||||
|
||||
@ -522,7 +522,7 @@
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (REGNO (op) != 61)
|
||||
if (REGNO (op) != CC_REG)
|
||||
return FALSE;
|
||||
if (mode == rmode
|
||||
|| (mode == CC_ZNmode && rmode == CC_Zmode)
|
||||
@ -609,7 +609,9 @@
|
||||
)
|
||||
|
||||
(define_predicate "noncommutative_operator"
|
||||
(ior (match_code "minus,ashift,ashiftrt,lshiftrt,rotatert")
|
||||
(ior (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
|
||||
(match_test "TARGET_BARREL_SHIFTER"))
|
||||
(match_code "minus")
|
||||
(and (match_code "ss_minus")
|
||||
(match_test "TARGET_ARC700 || TARGET_EA_SET")))
|
||||
)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user