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rs6000: Disable optimizing multiple xxsetaccz instructions into one xxsetaccz 

Fwprop will happily optimize two xxsetaccz instructions into one xxsetaccz
by propagating the results of the first to the uses of the second.
We really don't want that to happen given the late priming/depriming of
accumulators.  I fixed this by making the xxsetaccz source operand an
unspec volatile.  I also removed the mma_xxsetaccz define_expand and
define_insn_and_split and replaced it with a simple define_insn.
The expand and splitter patterns were leftovers from the pre opaque mode
code when the xxsetaccz code was part of the movpxi pattern, and we don't
need them now.

Rather than a new test case, I was able to just modify the current test case
to add another __builtin_mma_xxsetaccz call which shows the bad code gen
with unpatched compilers.

2021-09-14  Peter Bergner  <bergner@linux.ibm.com>

gcc/
	* config/rs6000/mma.md (unspec): Delete UNSPEC_MMA_XXSETACCZ.
	(unspecv): Add UNSPECV_MMA_XXSETACCZ.
	(*mma_xxsetaccz): Delete.
	(mma_xxsetaccz): Change to define_insn.  Remove operand 1.
	Use UNSPECV_MMA_XXSETACCZ.  Update comment.
	* config/rs6000/rs6000.c (rs6000_rtx_costs): Use UNSPECV_MMA_XXSETACCZ.

gcc/testsuite/
	* gcc.target/powerpc/mma-builtin-6.c: Add second call to xxsetacc
	built-in.  Update instruction counts.
This commit is contained in:
Peter Bergner 2021-09-14 10:47:18 -05:00
parent fb32372651
commit f80b9be083
3 changed files with 19 additions and 28 deletions
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31
gcc/config/rs6000/mma.md
View File

@ -91,7 +91,10 @@
UNSPEC_MMA_XVI8GER4SPP UNSPEC_MMA_XVI8GER4SPP
UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC UNSPEC_MMA_XXMTACC
UNSPEC_MMA_XXSETACCZ ])
(define_c_enum "unspecv"
[UNSPECV_MMA_XXSETACCZ
]) ])
;; MMA instructions with 1 accumulator argument ;; MMA instructions with 1 accumulator argument
@ -467,30 +470,16 @@
"<acc> %A0" "<acc> %A0"
[(set_attr "type" "mma")]) [(set_attr "type" "mma")])
;; We can't have integer constants in XOmode so we wrap this in an UNSPEC. ;; We can't have integer constants in XOmode so we wrap this in an
;; UNSPEC_VOLATILE.
(define_expand "mma_xxsetaccz" (define_insn "mma_xxsetaccz"
[(set (match_operand:XO 0 "fpr_reg_operand")
(const_int 0))]
"TARGET_MMA"
{
rtx xo0 = gen_rtx_UNSPEC (XOmode, gen_rtvec (1, const0_rtx),
UNSPEC_MMA_XXSETACCZ);
emit_insn (gen_rtx_SET (operands[0], xo0));
DONE;
})
(define_insn_and_split "*mma_xxsetaccz"
[(set (match_operand:XO 0 "fpr_reg_operand" "=d") [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
(unspec:XO [(match_operand 1 "const_0_to_1_operand" "O")] (unspec_volatile:XO [(const_int 0)]
UNSPEC_MMA_XXSETACCZ))] UNSPECV_MMA_XXSETACCZ))]
"TARGET_MMA" "TARGET_MMA"
"xxsetaccz %A0" "xxsetaccz %A0"
"&& reload_completed" [(set_attr "type" "mma")])
[(set (match_dup 0) (unspec:XO [(match_dup 1)] UNSPEC_MMA_XXSETACCZ))]
""
[(set_attr "type" "mma")
(set_attr "length" "4")])
(define_insn "mma_<vv>" (define_insn "mma_<vv>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d") [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")

2
gcc/config/rs6000/rs6000.c
View File

@ -22174,7 +22174,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
break; break;
case UNSPEC: case UNSPEC:
if (XINT (x, 1) == UNSPEC_MMA_XXSETACCZ) if (XINT (x, 1) == UNSPECV_MMA_XXSETACCZ)
{ {
*total = 0; *total = 0;
return true; return true;

14
gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c
View File

@ -5,14 +5,16 @@
void void
foo (__vector_quad *dst) foo (__vector_quad *dst)
{ {
__vector_quad acc; __vector_quad acc0, acc1;
__builtin_mma_xxsetaccz (&acc); __builtin_mma_xxsetaccz (&acc0);
*dst = acc; __builtin_mma_xxsetaccz (&acc1);
dst[0] = acc0;
dst[1] = acc1;
} }
/* { dg-final { scan-assembler-not {\mlxv\M} } } */ /* { dg-final { scan-assembler-not {\mlxv\M} } } */
/* { dg-final { scan-assembler-not {\mlxvp\M} } } */ /* { dg-final { scan-assembler-not {\mlxvp\M} } } */
/* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */ /* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */
/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxmfacc\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */ /* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */