arm.c: Include aarch-cost-tables.h.
* config/arm/arm.c: Include aarch-cost-tables.h. (generic_extra_costs): Move from here... * config/arm/aarch-cost-tables.h: ... To here. New file. From-SVN: r204735
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
47490470c6
commit
f819a56dc7
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@ -1,3 +1,9 @@
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2013-11-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.c: Include aarch-cost-tables.h.
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(generic_extra_costs): Move from here...
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* config/arm/aarch-cost-tables.h: ... To here. New file.
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2013-11-13 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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@ -0,0 +1,126 @@
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/* RTX cost tables shared between arm and aarch64.
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Copyright (C) 2013 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_AARCH_COST_TABLES_H
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#define GCC_AARCH_COST_TABLES_H
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const struct cpu_cost_table generic_extra_costs =
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{
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/* ALU */
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{
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0, /* Arith. */
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0, /* Logical. */
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0, /* Shift. */
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COSTS_N_INSNS (1), /* Shift_reg. */
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0, /* Arith_shift. */
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COSTS_N_INSNS (1), /* Arith_shift_reg. */
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0, /* Log_shift. */
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COSTS_N_INSNS (1), /* Log_shift_reg. */
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0, /* Extend. */
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COSTS_N_INSNS (1), /* Extend_arith. */
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0, /* Bfi. */
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0, /* Bfx. */
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0, /* Clz. */
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COSTS_N_INSNS (1), /* non_exec. */
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false /* non_exec_costs_exec. */
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},
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{
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/* MULT SImode */
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{
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COSTS_N_INSNS (2), /* Simple. */
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COSTS_N_INSNS (1), /* Flag_setting. */
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COSTS_N_INSNS (2), /* Extend. */
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COSTS_N_INSNS (3), /* Add. */
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COSTS_N_INSNS (3), /* Extend_add. */
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COSTS_N_INSNS (8) /* Idiv. */
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},
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/* MULT DImode */
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{
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0, /* Simple (N/A). */
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0, /* Flag_setting (N/A). */
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COSTS_N_INSNS (2), /* Extend. */
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0, /* Add (N/A). */
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COSTS_N_INSNS (3), /* Extend_add. */
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0 /* Idiv (N/A). */
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}
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},
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/* LD/ST */
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{
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COSTS_N_INSNS (2), /* Load. */
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COSTS_N_INSNS (2), /* Load_sign_extend. */
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COSTS_N_INSNS (3), /* Ldrd. */
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COSTS_N_INSNS (2), /* Ldm_1st. */
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1, /* Ldm_regs_per_insn_1st. */
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1, /* Ldm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Loadf. */
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COSTS_N_INSNS (3), /* Loadd. */
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COSTS_N_INSNS (1), /* Load_unaligned. */
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COSTS_N_INSNS (2), /* Store. */
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COSTS_N_INSNS (3), /* Strd. */
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COSTS_N_INSNS (2), /* Stm_1st. */
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1, /* Stm_regs_per_insn_1st. */
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1, /* Stm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Storef. */
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COSTS_N_INSNS (3), /* Stored. */
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COSTS_N_INSNS (1) /* Store_unaligned. */
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},
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{
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/* FP SFmode */
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{
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COSTS_N_INSNS (7), /* Div. */
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COSTS_N_INSNS (2), /* Mult. */
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COSTS_N_INSNS (3), /* Mult_addsub. */
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COSTS_N_INSNS (3), /* Fma. */
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COSTS_N_INSNS (1), /* Addsub. */
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0, /* Fpconst. */
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0, /* Neg. */
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0, /* Compare. */
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0, /* Widen. */
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0, /* Narrow. */
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0, /* Toint. */
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0, /* Fromint. */
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0 /* Roundint. */
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},
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/* FP DFmode */
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{
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COSTS_N_INSNS (15), /* Div. */
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COSTS_N_INSNS (5), /* Mult. */
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COSTS_N_INSNS (7), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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0, /* Fpconst. */
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0, /* Neg. */
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0, /* Compare. */
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0, /* Widen. */
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0, /* Narrow. */
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0, /* Toint. */
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0, /* Fromint. */
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0 /* Roundint. */
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}
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},
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/* Vector */
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{
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COSTS_N_INSNS (1) /* Alu. */
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}
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};
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#endif /* GCC_AARCH_COST_TABLES_H */
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@ -949,106 +949,9 @@ struct cpu_vec_costs arm_default_vec_cost = {
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1, /* cond_not_taken_branch_cost. */
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};
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/* Cost tables for AArch32 + AArch64 cores should go in aarch-cost-tables.h */
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#include "aarch-cost-tables.h"
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const struct cpu_cost_table generic_extra_costs =
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{
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/* ALU */
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{
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0, /* Arith. */
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0, /* Logical. */
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0, /* Shift. */
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COSTS_N_INSNS (1), /* Shift_reg. */
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0, /* Arith_shift. */
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COSTS_N_INSNS (1), /* Arith_shift_reg. */
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0, /* Log_shift. */
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COSTS_N_INSNS (1), /* Log_shift_reg. */
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0, /* Extend. */
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COSTS_N_INSNS (1), /* Extend_arith. */
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0, /* Bfi. */
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0, /* Bfx. */
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0, /* Clz. */
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COSTS_N_INSNS (1), /* non_exec. */
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false /* non_exec_costs_exec. */
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},
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/* MULT SImode */
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{
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{
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COSTS_N_INSNS (2), /* Simple. */
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COSTS_N_INSNS (1), /* Flag_setting. */
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COSTS_N_INSNS (2), /* Extend. */
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COSTS_N_INSNS (3), /* Add. */
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COSTS_N_INSNS (3), /* Extend_add. */
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COSTS_N_INSNS (8) /* Idiv. */
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},
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/* MULT DImode */
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{
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0, /* Simple (N/A). */
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0, /* Flag_setting (N/A). */
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COSTS_N_INSNS (2), /* Extend. */
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0, /* Add (N/A). */
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COSTS_N_INSNS (3), /* Extend_add. */
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0 /* Idiv (N/A). */
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}
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},
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/* LD/ST */
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{
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COSTS_N_INSNS (2), /* Load. */
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COSTS_N_INSNS (2), /* Load_sign_extend. */
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COSTS_N_INSNS (3), /* Ldrd. */
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COSTS_N_INSNS (2), /* Ldm_1st. */
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1, /* Ldm_regs_per_insn_1st. */
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1, /* Ldm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Loadf. */
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COSTS_N_INSNS (3), /* Loadd. */
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COSTS_N_INSNS (1), /* Load_unaligned. */
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COSTS_N_INSNS (2), /* Store. */
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COSTS_N_INSNS (3), /* Strd. */
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COSTS_N_INSNS (2), /* Stm_1st. */
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1, /* Stm_regs_per_insn_1st. */
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1, /* Stm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Storef. */
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COSTS_N_INSNS (3), /* Stored. */
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COSTS_N_INSNS (1) /* Store_unaligned. */
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},
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{
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/* FP SFmode */
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{
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COSTS_N_INSNS (7), /* Div. */
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COSTS_N_INSNS (2), /* Mult. */
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COSTS_N_INSNS (3), /* Mult_addsub. */
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COSTS_N_INSNS (3), /* Fma. */
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COSTS_N_INSNS (1), /* Addsub. */
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0, /* Fpconst. */
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0, /* Neg. */
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0, /* Compare. */
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0, /* Widen. */
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0, /* Narrow. */
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0, /* Toint. */
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0, /* Fromint. */
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0 /* Roundint. */
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},
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/* FP DFmode */
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{
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COSTS_N_INSNS (15), /* Div. */
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COSTS_N_INSNS (5), /* Mult. */
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COSTS_N_INSNS (7), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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0, /* Fpconst. */
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0, /* Neg. */
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0, /* Compare. */
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0, /* Widen. */
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0, /* Narrow. */
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0, /* Toint. */
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0, /* Fromint. */
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0 /* Roundint. */
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}
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},
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/* Vector */
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{
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COSTS_N_INSNS (1) /* Alu. */
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}
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};
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const struct cpu_cost_table cortexa9_extra_costs =
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