rs6000.c (rs6000_hard_regno_nregs): Adjust for e500 doubles.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs): Adjust for e500 doubles. (spe_build_register_parallel): New. (rs6000_spe_function_arg): Handle e500 doubles. (function_arg): Same. (spe_func_has_64bit_regs_p): Same. (rs6000_function_value): Same. (rs6000_libcall_value): Same. (legitimate_lo_sum_address_p): Return false for e500 doubles. * config/rs6000/rs6000.h (LOCAL_ALIGNMENT): Adjust for e500 doubles. (DATA_ALIGNMENT): Same. (CANNOT_CHANGE_MODE_CLASS): Same. From-SVN: r89582
This commit is contained in:
Aldy Hernandez
Aldy Hernandez
parent
8db8c940f1
commit
f82f556dac
@ -1,3 +1,20 @@
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2004-10-26 Aldy Hernandez <aldyh@redhat.com>
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* config/rs6000/rs6000.c (rs6000_hard_regno_nregs): Adjust for
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e500 doubles.
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(spe_build_register_parallel): New.
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(rs6000_spe_function_arg): Handle e500 doubles.
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(function_arg): Same.
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(spe_func_has_64bit_regs_p): Same.
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(rs6000_function_value): Same.
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(rs6000_libcall_value): Same.
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(legitimate_lo_sum_address_p): Return false for e500 doubles.
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* config/rs6000/rs6000.h (LOCAL_ALIGNMENT): Adjust for e500
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doubles.
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(DATA_ALIGNMENT): Same.
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(CANNOT_CHANGE_MODE_CLASS): Same.
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2004-10-26 Aldy Hernandez <aldyh@redhat.com>
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* expr.c (emit_group_load): Handle floats.
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@ -3281,6 +3281,8 @@ legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
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return false;
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if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
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return false;
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if (TARGET_E500_DOUBLE && mode == DFmode)
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return false;
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x = XEXP (x, 1);
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if (TARGET_ELF || TARGET_MACHO)
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@ -3418,8 +3420,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
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&& GET_CODE (x) != CONST_INT
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&& GET_CODE (x) != CONST_DOUBLE
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&& CONSTANT_P (x)
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&& ((TARGET_HARD_FLOAT && TARGET_FPRS)
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|| (mode != DFmode || TARGET_E500_DOUBLE))
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&& ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
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&& mode != DImode
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&& mode != TImode)
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{
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@ -4933,15 +4934,50 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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}
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}
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/* Determine where to put a SIMD argument on the SPE. */
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static rtx
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spe_build_register_parallel (enum machine_mode mode, int gregno)
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{
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rtx r1, r2;
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enum machine_mode inner;
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unsigned int inner_bytes;
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if (mode == DFmode)
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{
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inner = SImode;
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inner_bytes = 4;
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}
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else
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abort ();
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r1 = gen_rtx_REG (inner, gregno);
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r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
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r2 = gen_rtx_REG (inner, gregno + 1);
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r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (inner_bytes));
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return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
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}
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/* Determine where to put a SIMD argument on the SPE. */
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static rtx
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rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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tree type)
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{
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int gregno = cum->sysv_gregno;
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/* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
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are passed and returned in a pair of GPRs for ABI compatability. */
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if (TARGET_E500_DOUBLE && mode == DFmode)
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{
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/* Doubles go in an odd/even register pair (r5/r6, etc). */
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gregno += (1 - gregno) & 1;
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/* We do not split between registers and stack. */
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if (gregno + 1 > GP_ARG_MAX_REG)
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return NULL_RTX;
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return spe_build_register_parallel (mode, gregno);
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}
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if (cum->stdarg)
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{
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int gregno = cum->sysv_gregno;
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int n_words = rs6000_arg_size (mode, type);
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/* SPE vectors are put in odd registers. */
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@ -4964,8 +5000,8 @@ rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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}
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else
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{
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if (cum->sysv_gregno <= GP_ARG_MAX_REG)
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return gen_rtx_REG (mode, cum->sysv_gregno);
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if (gregno <= GP_ARG_MAX_REG)
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return gen_rtx_REG (mode, gregno);
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else
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return NULL_RTX;
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}
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@ -5144,7 +5180,9 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
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}
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}
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else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
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else if (TARGET_SPE_ABI && TARGET_SPE
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&& (SPE_VECTOR_MODE (mode)
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|| (TARGET_E500_DOUBLE && mode == DFmode)))
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return rs6000_spe_function_arg (cum, mode, type);
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else if (abi == ABI_V4)
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{
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@ -12543,9 +12581,15 @@ spe_func_has_64bit_regs_p (void)
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rtx i;
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i = PATTERN (insn);
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if (GET_CODE (i) == SET
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&& SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
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return true;
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if (GET_CODE (i) == SET)
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{
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enum machine_mode mode = GET_MODE (SET_SRC (i));
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if (SPE_VECTOR_MODE (mode))
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return true;
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if (TARGET_E500_DOUBLE && mode == DFmode)
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return true;
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}
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}
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}
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@ -18078,6 +18122,8 @@ rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
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&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
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&& ALTIVEC_VECTOR_MODE(mode))
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regno = ALTIVEC_ARG_RETURN;
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else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
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return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
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else
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regno = GP_ARG_RETURN;
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@ -18113,6 +18159,8 @@ rs6000_libcall_value (enum machine_mode mode)
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regno = ALTIVEC_ARG_RETURN;
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else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
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return rs6000_complex_function_value (mode);
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else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
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return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
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else
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regno = GP_ARG_RETURN;
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@ -742,6 +742,7 @@ extern const char *rs6000_warn_altivec_long_switch;
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that the object would ordinarily have. */
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#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
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((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
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(TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
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(TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
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/* Alignment of field after `int : 0' in a structure. */
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@ -774,9 +775,11 @@ extern const char *rs6000_warn_altivec_long_switch;
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: (ALIGN))
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/* Make arrays of chars word-aligned for the same reasons.
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Align vectors to 128 bits. */
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Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
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64 bits. */
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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(TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
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: (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
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: TREE_CODE (TYPE) == ARRAY_TYPE \
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&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
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&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
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@ -1433,6 +1436,8 @@ enum reg_class
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? 0 \
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: GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
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? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
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: (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
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? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
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: (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
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? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
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: 0)
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