v850.md (addsi3_set_flags): New pattern.
* config/v850/v850.md (addsi3_set_flags): New pattern. (subsi3_set_flags, negsi2_set_flags, andsi3_set_flags): Likewise. (iorsi3_set_flags, xorsi3_set_flags, one_cmplsi2_set_flags): Likewise. (zero_extendhisi2_v850_set_flags): Likewise. (zero_extendqisi2_v850_set_flags): Likewise. (ashlsi3_set_flags, ashlsi3_v850e2_set_flags): Likewise. (lshrsi3_set_flags, lshrsi3_v850e2_set_flags): Likewise. (ashrsi3_set_flags, ashrsi3_v850e2_set_flags): Likewise. Co-Authored-By: Austin Law <austinklaw@gmail.com> From-SVN: r262192
This commit is contained in:
parent
1ec0eb08ce
commit
f8dc0f2bf4
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@ -1,6 +1,15 @@
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2018-06-27 Jeff Law <law@redhat.com>
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Austin Law <austinklaw@gmail.com>
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* config/v850/v850.md (addsi3_set_flags): New pattern.
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(subsi3_set_flags, negsi2_set_flags, andsi3_set_flags): Likewise.
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(iorsi3_set_flags, xorsi3_set_flags, one_cmplsi2_set_flags): Likewise.
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(zero_extendhisi2_v850_set_flags): Likewise.
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(zero_extendqisi2_v850_set_flags): Likewise.
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(ashlsi3_set_flags, ashlsi3_v850e2_set_flags): Likewise.
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(lshrsi3_set_flags, lshrsi3_v850e2_set_flags): Likewise.
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(ashrsi3_set_flags, ashrsi3_v850e2_set_flags): Likewise.
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* config/v850/v850-protos.h (notice_update_cc): Remove.
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* config/v850/v850.c (v850_compare_op0, v850_compare_op1): Remove.
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(v850_print_operand): Handle 'D' and "d".
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@ -569,6 +569,20 @@
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addi %O2(%P2),%1,%0"
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[(set_attr "length" "2,4,4")])
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(define_insn "addsi3_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
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(match_operand:SI 2 "nonmemory_operand" "rJ,K,U"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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add %2,%0
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addi %2,%1,%0
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addi %O2(%P2),%1,%0"
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[(set_attr "length" "2,4,4")])
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;; ----------------------------------------------------------------------
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;; SUBTRACT INSTRUCTIONS
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;; ----------------------------------------------------------------------
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@ -593,6 +607,19 @@
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subr %1,%0"
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[(set_attr "length" "2,2")])
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(define_insn "*subsi3_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
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(match_operand:SI 2 "nonmemory_operand" "r,0"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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sub %2,%0
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subr %1,%0"
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[(set_attr "length" "2,2")])
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(define_insn_and_split "negsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "0")))]
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@ -610,6 +637,16 @@
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"subr %.,%0"
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[(set_attr "length" "2")])
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(define_insn "*negsi2_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (neg:SI (match_operand:SI 1 "register_operand" "0"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_dup 1)))]
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"reload_completed"
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"subr %.,%0"
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[(set_attr "length" "2")])
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;; ----------------------------------------------------------------------
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;; MULTIPLY INSTRUCTIONS
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;; ----------------------------------------------------------------------
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@ -831,6 +868,20 @@
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andi %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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(define_insn "andsi3_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
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(match_operand:SI 2 "nonmemory_operand" "r,I,M"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(and:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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and %2,%0
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and %.,%0
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andi %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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;; ----------------------------------------------------------------------
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;; OR INSTRUCTIONS
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;; ----------------------------------------------------------------------
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@ -916,6 +967,20 @@
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ori %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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(define_insn "*iorsi3_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
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(match_operand:SI 2 "nonmemory_operand" "r,I,M"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(ior:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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or %2,%0
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or %.,%0
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ori %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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;; ----------------------------------------------------------------------
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;; XOR INSTRUCTIONS
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;; ----------------------------------------------------------------------
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@ -1001,6 +1066,20 @@
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xori %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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(define_insn "*xorsi3_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
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(match_operand:SI 2 "nonmemory_operand" "r,I,M"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(xor:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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xor %2,%0
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xor %.,%0
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xori %2,%1,%0"
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[(set_attr "length" "2,2,4")])
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;; ----------------------------------------------------------------------
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;; NOT INSTRUCTIONS
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@ -1024,6 +1103,16 @@
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"not %1,%0"
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[(set_attr "length" "2")])
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(define_insn "*one_cmplsi2_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (not:SI (match_operand:SI 1 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(not:SI (match_dup 1)))]
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"reload_completed"
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"not %1,%0"
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[(set_attr "length" "2")])
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;; -----------------------------------------------------------------
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;; BIT FIELDS
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;; -----------------------------------------------------------------
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"andi 65535,%1,%0"
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[(set_attr "length" "4")])
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(define_insn "*zero_extendhisi2_v850_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_dup 1)))]
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"reload_completed"
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"andi 65535,%1,%0"
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[(set_attr "length" "4")])
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(define_expand "zero_extendhisi2"
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[(parallel [(set (match_operand:SI 0 "register_operand")
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(zero_extend:SI
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@ -1841,6 +1940,16 @@
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"andi 255,%1,%0"
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[(set_attr "length" "4")])
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(define_insn "*zero_extendqisi2_v850_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_dup 1)))]
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"reload_completed"
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"andi 255,%1,%0"
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[(set_attr "length" "4")])
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(define_expand "zero_extendqisi2"
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[(parallel [(set (match_operand:SI 0 "register_operand")
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(zero_extend:SI
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shl %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "ashlsi3_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,N"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r")
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(ashift:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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shl %2,%0
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shl %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "ashlsi3_v850e2_clobber_flags"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashift:SI
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"shl %2,%1,%0"
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[(set_attr "length" "4")])
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(define_insn "ashlsi3_v850e2_set_flags"
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[(set (reg:CCNZ CC_REGNUM)
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(compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "nonmemory_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(ashift:SI (match_dup 1) (match_dup 2)))]
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"reload_completed && TARGET_V850E2_UP"
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"shl %2,%1,%0"
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[(set_attr "length" "4")])
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(define_insn_and_split "lshrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(lshiftrt:SI
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shr %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "lshrsi3_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,N"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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shr %2,%0
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shr %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "lshrsi3_v850e2_clobber_flags"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(lshiftrt:SI
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"shr %2,%1,%0"
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[(set_attr "length" "4")])
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(define_insn "lshrsi3_v850e2_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "nonmemory_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"reload_completed && TARGET_V850E2_UP"
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"shr %2,%1,%0"
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[(set_attr "length" "4")])
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(define_insn_and_split "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(ashiftrt:SI
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sar %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "ashrsi3_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,N"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r,r")
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(ashiftrt:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"@
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sar %2,%0
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sar %2,%0"
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[(set_attr "length" "4,2")])
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(define_insn "ashrsi3_v850e2_clobber_flags"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashiftrt:SI
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"sar %2,%1,%0"
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[(set_attr "length" "4")])
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(define_insn "ashrsi3_v850e2_set_flags"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "nonmemory_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(ashiftrt:SI (match_dup 1) (match_dup 2)))]
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"reload_completed && TARGET_V850E2_UP"
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"sar %2,%1,%0"
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[(set_attr "length" "4")])
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;; ----------------------------------------------------------------------
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;; FIND FIRST BIT INSTRUCTION
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;; ----------------------------------------------------------------------
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