alpha: Introduce target specific store_data_bypass_p function [PR105209]
This patch introduces alpha-specific version of store_data_bypass_p that
ignores TRAP_IF that would result in assertion failure (and internal
compiler error) in the generic store_data_bypass_p function.
While at it, also remove ev4_ist_c reservation, store_data_bypass_p
can handle the patterns with multiple sets since some time ago.
2022-06-17 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/105209
* config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New.
* config/alpha/alpha.cc (alpha_store_data_bypass_p): New function.
(alpha_store_data_bypass_p_1): Ditto.
* config/alpha/ev4.md: Use alpha_store_data_bypass_p instead
of generic store_data_bypass_p.
(ev4_ist_c): Remove insn reservation.
gcc/testsuite/ChangeLog:
PR target/105209
* gcc.target/alpha/pr105209.c: New test.
(cherry picked from commit cc378e6557
)
This commit is contained in:
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@ -73,6 +73,8 @@ extern void alpha_end_function (FILE *, const char *, tree);
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extern bool alpha_find_lo_sum_using_gp (rtx);
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extern int alpha_store_data_bypass_p (rtx_insn *, rtx_insn *);
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#ifdef REAL_VALUE_TYPE
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extern int check_float_value (machine_mode, REAL_VALUE_TYPE *, int);
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#endif
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@ -7564,6 +7564,75 @@ alpha_does_function_need_gp (void)
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return 0;
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}
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/* Helper function for alpha_store_data_bypass_p, handle just a single SET
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IN_SET. */
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static bool
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alpha_store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set)
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{
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if (!MEM_P (SET_DEST (in_set)))
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return false;
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rtx out_set = single_set (out_insn);
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if (out_set)
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return !reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set));
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rtx out_pat = PATTERN (out_insn);
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if (GET_CODE (out_pat) != PARALLEL)
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return false;
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for (int i = 0; i < XVECLEN (out_pat, 0); i++)
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{
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rtx out_exp = XVECEXP (out_pat, 0, i);
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if (GET_CODE (out_exp) == CLOBBER || GET_CODE (out_exp) == USE
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|| GET_CODE (out_exp) == TRAP_IF)
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continue;
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gcc_assert (GET_CODE (out_exp) == SET);
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if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
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return false;
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}
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return true;
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}
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/* True if the dependency between OUT_INSN and IN_INSN is on the store
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data not the address operand(s) of the store. IN_INSN and OUT_INSN
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must be either a single_set or a PARALLEL with SETs inside.
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This alpha-specific version of store_data_bypass_p ignores TRAP_IF
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that would result in assertion failure (and internal compiler error)
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in the generic store_data_bypass_p function. */
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int
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alpha_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
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{
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rtx in_set = single_set (in_insn);
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if (in_set)
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return alpha_store_data_bypass_p_1 (out_insn, in_set);
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rtx in_pat = PATTERN (in_insn);
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if (GET_CODE (in_pat) != PARALLEL)
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return false;
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for (int i = 0; i < XVECLEN (in_pat, 0); i++)
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{
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rtx in_exp = XVECEXP (in_pat, 0, i);
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if (GET_CODE (in_exp) == CLOBBER || GET_CODE (in_exp) == USE
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|| GET_CODE (in_exp) == TRAP_IF)
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continue;
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gcc_assert (GET_CODE (in_exp) == SET);
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if (!alpha_store_data_bypass_p_1 (out_insn, in_exp))
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return false;
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}
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return true;
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}
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/* Helper function to set RTX_FRAME_RELATED_P on instructions, including
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sequences. */
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@ -44,14 +44,7 @@
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; Stores can issue before the data (but not address) is ready.
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(define_insn_reservation "ev4_ist" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "ist"))
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"ev4_ib1+ev4_abox")
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; ??? Separate from ev4_ist because store_data_bypass_p can't handle
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; the patterns with multiple sets, like store-conditional.
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(define_insn_reservation "ev4_ist_c" 1
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(and (eq_attr "tune" "ev4")
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(eq_attr "type" "st_c"))
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(eq_attr "type" "ist,st_c"))
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"ev4_ib1+ev4_abox")
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(define_insn_reservation "ev4_fst" 1
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@ -110,7 +103,7 @@
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(define_bypass 0
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"ev4_iaddlog,ev4_shiftcm,ev4_icmp"
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"ev4_ist"
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"store_data_bypass_p")
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"alpha_store_data_bypass_p")
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; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can
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; be issued exactly three cycles before an integer multiply completes".
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@ -121,7 +114,7 @@
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(eq_attr "opsize" "si")))
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"ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox")
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(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p")
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(define_bypass 20 "ev4_imulsi" "ev4_ist" "alpha_store_data_bypass_p")
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(define_insn_reservation "ev4_imuldi" 23
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(and (eq_attr "tune" "ev4")
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@ -129,7 +122,7 @@
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(eq_attr "opsize" "!si")))
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"ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox")
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(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p")
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(define_bypass 22 "ev4_imuldi" "ev4_ist" "alpha_store_data_bypass_p")
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; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in.
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(define_insn_reservation "ev4_fpop" 6
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@ -0,0 +1,26 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftrapv -mcpu=ev4" } */
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typedef struct tnode_t {
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struct tnode_t *tn_left, *tn_right;
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int v_quad;
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} tnode_t;
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int constant_addr(const tnode_t *, long *);
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int constant_addr(const tnode_t *tn, long *offsp)
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{
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long offs1 = 0, offs2 = 0;
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if (tn->v_quad > 0) {
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offs1 = tn->v_quad;
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return 0;
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} else if (tn->v_quad > -1) {
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offs2 = tn->tn_right->v_quad;
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if (!constant_addr(tn->tn_left, &offs1))
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return 0;
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} else {
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return 0;
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}
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*offsp = offs1 + offs2;
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return 1;
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}
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