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Turn HARD_REGNO_MODE_OK into a target hook 

2017-09-04  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* target.def (hard_regno_mode_ok): New hook.
	* doc/tm.texi (HARD_REGNO_MODE_OK): Replace with...
	(TARGET_HARD_REGNO_MODE_OK): ...this.
	* doc/tm.texi.in: Regenerate.
	* hooks.h (hook_bool_uint_mode_true): Declare.
	* hooks.c (hook_bool_uint_mode_true): New function.
	* doc/md.texi: Refer to targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* genpreds.c (write_insn_preds_c): Add an include of target.h.
	* alias.c (init_alias_target): Use targetm.hard_regno_mode_ok
	instead of HARD_REGNO_MODE_OK.
	* caller-save.c: Include target.h.
	(reg_save_code): Use targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* combine.c (can_combine_p): Likewise.
	(combinable_i3pat): Likewise.
	(can_change_dest_mode): Likewise.
	* expr.c (init_expr_target): Likewise.
	(convert_move): Likewise.
	(convert_modes): Likewise.
	* ira.c (setup_prohibited_class_mode_regs): Likewise.
	(setup_prohibited_mode_move_regs): Likewise.
	* ira.h (target_ira): Likewise.
	* lra-assigns.c (find_hard_regno_for_1): Likewise.
	* lra-constraints.c (process_alt_operands): Likewise.
	(split_reg): Likewise.
	* recog.c (peep2_find_free_register): Likewise.
	* ree.c (combine_reaching_defs): Likewise.
	* regcprop.c (maybe_mode_change): Likewise.
	* reginfo.c (init_reg_sets_1): Likewise.
	(choose_hard_reg_mode): Likewise.
	(simplifiable_subregs): Likewise.
	* regrename.c (check_new_reg_p): Likewise.
	* reload.c (find_valid_class): Likewise.
	(find_valid_class_1): Likewise.
	(reload_inner_reg_of_subreg): Likewise.
	(push_reload): Likewise.
	(combine_reloads): Likewise.
	(find_dummy_reload): Likewise.
	(find_reloads): Likewise.
	* reload1.c (find_reg): Likewise.
	(set_reload_reg): Likewise.
	(allocate_reload_reg): Likewise.
	(choose_reload_regs): Likewise.
	(reload_adjust_reg_for_temp): Likewise.
	* rtlanal.c (subreg_size_offset_from_lsb): Likewise.
	(simplify_subreg_regno): Likewise.
	* sel-sched.c (init_regs_for_mode): Likewise.
	* varasm.c (make_decl_rtl): Likewise.
	* config/aarch64/aarch64.h (HARD_REGNO_MODE_OK): Delete.
	(MODES_TIEABLE_P): Use targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* config/aarch64/aarch64-protos.h (aarch64_hard_regno_mode_ok): Delete.
	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/alpha/alpha.h (HARD_REGNO_MODE_OK): Delete.
	* config/alpha/alpha.c (alpha_hard_regno_mode_ok): New function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/arc/arc.h (arc_hard_regno_mode_ok): Delete.
	(arc_mode_class): Delete.
	(HARD_REGNO_MODE_OK): Delete.
	* config/arc/arc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(arc_hard_regno_mode_ok): Rename old array to...
	(arc_hard_regno_mode_ok_modes): ...this.
	(arc_conditional_register_usage): Update accordingly.
	(arc_mode_class): Make static.
	(arc_hard_regno_mode_ok): New function.
	* config/arm/arm.h (HARD_REGNO_MODE_OK): Delete.
	* config/arm/arm-protos.h (arm_hard_regno_mode_ok): Delete.
	* config/arm/arm.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(arm_hard_regno_mode_ok): Make static.
	* config/arm/arm.md (movdi): Use targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* config/avr/avr-protos.h (avr_hard_regno_mode_ok): Delete.
	* config/avr/avr.h (HARD_REGNO_MODE_OK): Delete.
	* config/avr/avr.c (avr_hard_regno_mode_ok): Make static and
	return a bool.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/bfin/bfin-protos.h (hard_regno_mode_ok): Delete.
	* config/bfin/bfin.h (HARD_REGNO_MODE_OK): Delete.
	* config/bfin/bfin.c (hard_regno_mode_ok): Rename to...
	(bfin_hard_regno_mode_ok): ...this.  Make static and return a bool.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/bfin/predicates.md (valid_reg_operand): Use
	targetm.hard_regno_mode_ok instead of HARD_REGNO_MODE_OK.
	* config/c6x/c6x.h (HARD_REGNO_MODE_OK): Delete.
	* config/c6x/c6x.c (c6x_hard_regno_mode_ok): New function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/cr16/cr16.h (HARD_REGNO_MODE_OK): Delete.
	* config/cr16/cr16-protos.h (cr16_hard_regno_mode_ok): Delete.
	* config/cr16/cr16.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(cr16_hard_regno_mode_ok): Make static and return a bool.
	* config/cris/cris.h (HARD_REGNO_MODE_OK): Delete.
	* config/cris/cris.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(cris_hard_regno_mode_ok): New function.
	* config/epiphany/epiphany.h (epiphany_hard_regno_mode_ok): Delete.
	(epiphany_mode_class): Delete.
	(HARD_REGNO_MODE_OK): Delete.
	* config/epiphany/epiphany-protos.h (hard_regno_mode_ok): Delete.
	* config/epiphany/epiphany.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(hard_regno_mode_ok): Rename to...
	(epiphany_hard_regno_mode_ok): ...this.  Make static and return a bool.
	* config/fr30/fr30.h (HARD_REGNO_MODE_OK): Delete.
	* config/fr30/fr30.md: Refer to targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* config/frv/frv.h (HARD_REGNO_MODE_OK): Delete.
	* config/frv/frv-protos.h (frv_hard_regno_mode_ok): Delete.
	* config/frv/frv.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(frv_hard_regno_mode_ok): Make static and return a bool.
	* config/frv/frv.md: Refer to targetm.hard_regno_mode_ok instead of
	HARD_REGNO_MODE_OK.
	* config/ft32/ft32.h (HARD_REGNO_MODE_OK): Delete.
	* config/h8300/h8300.h (HARD_REGNO_MODE_OK): Delete.
	* config/h8300/h8300-protos.h (h8300_hard_regno_mode_ok): Delete.
	* config/h8300/h8300.c (h8300_hard_regno_mode_ok): Make static
	and return a bool.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/i386/i386.h (HARD_REGNO_MODE_OK): Delete.
	* config/i386/i386-protos.h (ix86_hard_regno_mode_ok): Delete.
	* config/i386/i386.c (ix86_hard_regno_mode_ok): Make static and
	return a bool.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/ia64/ia64.h (HARD_REGNO_MODE_OK): Delete.
	* config/ia64/ia64.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(ia64_hard_regno_mode_ok): New function.
	* config/iq2000/iq2000.h (HARD_REGNO_MODE_OK): Delete.
	* config/iq2000/iq2000.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(iq2000_hard_regno_mode_ok): New function.
	* config/lm32/lm32.h (HARD_REGNO_MODE_OK): Delete.
	* config/lm32/lm32.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(lm32_hard_regno_mode_ok): New function.
	* config/m32c/m32c.h (HARD_REGNO_MODE_OK): Delete.
	* config/m32c/m32c-protos.h (m32c_hard_regno_ok): Delete.
	* config/m32c/m32c.c (class_can_hold_mode): Use m32c_hard_regno_mode_ok
	instead of HARD_REGNO_MODE_OK.
	(m32c_hard_regno_ok): Rename to...
	(m32c_hard_regno_mode_ok): ...this.  Make static and return a bool.
	(m32c_cannot_change_mode_class): Update accordingly.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/m32r/m32r.h (m32r_hard_regno_mode_ok): Delete.
	(m32r_mode_class): Delete.
	(HARD_REGNO_MODE_OK): Delete.
	* config/m32r/m32r.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(m32r_hard_regno_mode_ok): Rename to...
	(m32r_hard_regno_modes): ...this.
	(m32r_mode_class): Make static.
	(m32r_hard_regno_mode_ok): New function.
	* config/m68k/m68k.h (HARD_REGNO_MODE_OK): Delete.
	* config/m68k/m68k-protos.h (m68k_regno_mode_ok): Delete.
	* config/m68k/m68k.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(m68k_hard_regno_mode_ok): Make static.
	* config/mcore/mcore.h (HARD_REGNO_MODE_OK): Delete.
	* config/mcore/mcore.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(mcore_hard_regno_mode_ok): New function.
	* config/microblaze/microblaze.h (microblaze_hard_regno_mode_ok)
	(HARD_REGNO_MODE_OK): Delete.
	* config/microblaze/microblaze.c (microblaze_hard_regno_mode_ok):
	Rename to...
	(microblaze_hard_regno_mode_ok_p): ...this and make static.
	(microblaze_hard_regno_mode_ok): New function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/mips/mips.h (HARD_REGNO_MODE_OK): Delete.
	(mips_hard_regno_mode_ok): Delete.
	* config/mips/mips.c (mips_hard_regno_mode_ok): Rename to...
	(mips_hard_regno_mode_ok_p): ...this and make static.
	(mips_hard_regno_mode_ok_p): Rename to...
	(mips_hard_regno_mode_ok_uncached): ...this.
	(mips_hard_regno_mode_ok): New function.
	(mips_class_max_nregs): Use mips_hard_regno_mode_ok instead
	of HARD_REGNO_MODE_OK.
	(mips_option_override): Update after above name changes.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/mmix/mmix.h (HARD_REGNO_MODE_OK): Delete.
	* config/mn10300/mn10300.h (HARD_REGNO_MODE_OK): Delete.
	* config/mn10300/mn10300-protos.h (mn10300_hard_regno_mode_ok): Delete.
	* config/mn10300/mn10300.c (mn10300_hard_regno_mode_ok): Make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/moxie/moxie.h (HARD_REGNO_MODE_OK): Delete.
	* config/msp430/msp430.h (HARD_REGNO_MODE_OK): Delete.
	* config/msp430/msp430-protos.h (msp430_hard_regno_mode_ok): Delete.
	* config/msp430/msp430.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(msp430_hard_regno_mode_ok): Make static and return a bool.
	* config/nds32/nds32.h (HARD_REGNO_MODE_OK): Delete.
	* config/nds32/nds32-protos.h (nds32_hard_regno_mode_ok): Delete.
	* config/nds32/nds32.c (nds32_hard_regno_mode_ok): Make static
	and return a bool.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/nios2/nios2.h (HARD_REGNO_MODE_OK): Delete.
	* config/nvptx/nvptx.h (HARD_REGNO_MODE_OK): Delete.
	* config/pa/pa.h (MODES_TIEABLE_P): Update commentary.
	* config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): Rename to...
	(PA_HARD_REGNO_MODE_OK): ...this
	* config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Rename to...
	(PA_HARD_REGNO_MODE_OK): ...this.
	* config/pa/pa.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(pa_hard_regno_mode_ok): New function.
	* config/pdp11/pdp11.h (HARD_REGNO_MODE_OK): Delete.
	* config/pdp11/pdp11.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(pdp11_hard_regno_mode_ok): New function.
	* config/powerpcspe/powerpcspe.h (HARD_REGNO_MODE_OK): Delete.
	* config/powerpcspe/powerpcspe-protos.h (rs6000_hard_regno_mode_ok_p):
	Delete.
	* config/powerpcspe/powerpcspe.c (rs6000_hard_regno_mode_ok_p):
	Make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	(rs6000_hard_regno_mode_ok): Rename to...
	(rs6000_hard_regno_mode_ok_uncached): ...this.
	(rs6000_init_hard_regno_mode_ok): Update accordingly.
	(rs6000_hard_regno_mode_ok): New function.
	* config/riscv/riscv.h (HARD_REGNO_MODE_OK): Delete.
	* config/riscv/riscv-protos.h (riscv_hard_regno_mode_ok_p): Delete.
	* config/riscv/riscv.c (riscv_hard_regno_mode_ok_p): Rename to...
	(riscv_hard_regno_mode_ok): ...this and make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/rl78/rl78.h (HARD_REGNO_MODE_OK): Delete.
	* config/rl78/rl78-protos.h (rl78_hard_regno_mode_ok): Delete.
	* config/rl78/rl78.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(rl78_hard_regno_mode_ok): Make static and return bool.
	* config/rs6000/rs6000.h (HARD_REGNO_MODE_OK): Delete.
	* config/rs6000/rs6000-protos.h (rs6000_hard_regno_mode_ok_p):
	Delete.
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok_p): Make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	(rs6000_hard_regno_mode_ok): Rename to...
	(rs6000_hard_regno_mode_ok_uncached): ...this.
	(rs6000_init_hard_regno_mode_ok): Update accordingly.
	(rs6000_hard_regno_mode_ok): New function.
	* config/rx/rx.h (HARD_REGNO_MODE_OK): Delete.
	* config/rx/rx.c (rx_hard_regno_mode_ok): New function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/s390/s390.h (HARD_REGNO_MODE_OK): Delete.
	* config/s390/s390-protos.h (s390_hard_regno_mode_ok): Delete.
	* config/s390/s390.c (s390_hard_regno_mode_ok): Make static.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/sh/sh.h (HARD_REGNO_MODE_OK): Delete.
	* config/sh/sh-protos.h (sh_hard_regno_mode_ok): Delete.
	* config/sh/sh.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(sh_hard_regno_mode_ok): Make static.
	* config/sparc/constraints.md: Refer to targetm.hard_regno_mode_ok
	instead of HARD_REGNO_MODE_OK.
	* config/sparc/sparc.h (hard_regno_mode_classes): Delete.
	(sparc_mode_class): Delete.
	(HARD_REGNO_MODE_OK): Delete.
	* config/sparc/sparc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(hard_regno_mode_classes): Make static.
	(sparc_mode_class): Likewise.
	(sparc_hard_regno_mode_ok): New function.
	* config/spu/spu.h (HARD_REGNO_MODE_OK): Delete.
	* config/stormy16/stormy16.h (HARD_REGNO_MODE_OK): Delete.
	* config/stormy16/stormy16.c (xstormy16_hard_regno_mode_ok): New
	function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/tilegx/tilegx.h (HARD_REGNO_MODE_OK): Delete.
	* config/tilepro/tilepro.h (HARD_REGNO_MODE_OK): Delete.
	* config/v850/v850.h (HARD_REGNO_MODE_OK): Delete.
	* config/v850/v850.c (v850_hard_regno_mode_ok): New function.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	* config/vax/vax.h (HARD_REGNO_MODE_OK): Delete.
	* config/visium/visium.h (HARD_REGNO_MODE_OK): Delete.
	* config/visium/visium.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
	(visium_hard_regno_mode_ok): New function.
	* config/visium/visium.md: Refer to targetm.hard_regno_mode_ok
	instead of HARD_REGNO_MODE_OK.
	* config/xtensa/xtensa.h (xtensa_hard_regno_mode_ok): Delete.
	(HARD_REGNO_MODE_OK): Delete.
	* config/xtensa/xtensa.c (xtensa_hard_regno_mode_ok): Rename to...
	(xtensa_hard_regno_mode_ok_p): ...this and make static.
	(xtensa_option_override): Update accordingly.
	(TARGET_HARD_REGNO_MODE_OK): Redefine.
	(xtensa_hard_regno_mode_ok): New function.
	* system.h (HARD_REGNO_MODE_OK): Poison.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251646
This commit is contained in:
Richard Sandiford 2017-09-04 10:49:59 +00:00 committed by Richard Sandiford
parent 80ec73f4ee
commit f939c3e63c
143 changed files with 1046 additions and 760 deletions
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@ -1,3 +1,279 @@
2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* target.def (hard_regno_mode_ok): New hook.
* doc/tm.texi (HARD_REGNO_MODE_OK): Replace with...
(TARGET_HARD_REGNO_MODE_OK): ...this.
* doc/tm.texi.in: Regenerate.
* hooks.h (hook_bool_uint_mode_true): Declare.
* hooks.c (hook_bool_uint_mode_true): New function.
* doc/md.texi: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* genpreds.c (write_insn_preds_c): Add an include of target.h.
* alias.c (init_alias_target): Use targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* caller-save.c: Include target.h.
(reg_save_code): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* combine.c (can_combine_p): Likewise.
(combinable_i3pat): Likewise.
(can_change_dest_mode): Likewise.
* expr.c (init_expr_target): Likewise.
(convert_move): Likewise.
(convert_modes): Likewise.
* ira.c (setup_prohibited_class_mode_regs): Likewise.
(setup_prohibited_mode_move_regs): Likewise.
* ira.h (target_ira): Likewise.
* lra-assigns.c (find_hard_regno_for_1): Likewise.
* lra-constraints.c (process_alt_operands): Likewise.
(split_reg): Likewise.
* recog.c (peep2_find_free_register): Likewise.
* ree.c (combine_reaching_defs): Likewise.
* regcprop.c (maybe_mode_change): Likewise.
* reginfo.c (init_reg_sets_1): Likewise.
(choose_hard_reg_mode): Likewise.
(simplifiable_subregs): Likewise.
* regrename.c (check_new_reg_p): Likewise.
* reload.c (find_valid_class): Likewise.
(find_valid_class_1): Likewise.
(reload_inner_reg_of_subreg): Likewise.
(push_reload): Likewise.
(combine_reloads): Likewise.
(find_dummy_reload): Likewise.
(find_reloads): Likewise.
* reload1.c (find_reg): Likewise.
(set_reload_reg): Likewise.
(allocate_reload_reg): Likewise.
(choose_reload_regs): Likewise.
(reload_adjust_reg_for_temp): Likewise.
* rtlanal.c (subreg_size_offset_from_lsb): Likewise.
(simplify_subreg_regno): Likewise.
* sel-sched.c (init_regs_for_mode): Likewise.
* varasm.c (make_decl_rtl): Likewise.
* config/aarch64/aarch64.h (HARD_REGNO_MODE_OK): Delete.
(MODES_TIEABLE_P): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/aarch64/aarch64-protos.h (aarch64_hard_regno_mode_ok): Delete.
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/alpha/alpha.h (HARD_REGNO_MODE_OK): Delete.
* config/alpha/alpha.c (alpha_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/arc/arc.h (arc_hard_regno_mode_ok): Delete.
(arc_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/arc/arc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(arc_hard_regno_mode_ok): Rename old array to...
(arc_hard_regno_mode_ok_modes): ...this.
(arc_conditional_register_usage): Update accordingly.
(arc_mode_class): Make static.
(arc_hard_regno_mode_ok): New function.
* config/arm/arm.h (HARD_REGNO_MODE_OK): Delete.
* config/arm/arm-protos.h (arm_hard_regno_mode_ok): Delete.
* config/arm/arm.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(arm_hard_regno_mode_ok): Make static.
* config/arm/arm.md (movdi): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/avr/avr-protos.h (avr_hard_regno_mode_ok): Delete.
* config/avr/avr.h (HARD_REGNO_MODE_OK): Delete.
* config/avr/avr.c (avr_hard_regno_mode_ok): Make static and
return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/bfin/bfin-protos.h (hard_regno_mode_ok): Delete.
* config/bfin/bfin.h (HARD_REGNO_MODE_OK): Delete.
* config/bfin/bfin.c (hard_regno_mode_ok): Rename to...
(bfin_hard_regno_mode_ok): ...this. Make static and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/bfin/predicates.md (valid_reg_operand): Use
targetm.hard_regno_mode_ok instead of HARD_REGNO_MODE_OK.
* config/c6x/c6x.h (HARD_REGNO_MODE_OK): Delete.
* config/c6x/c6x.c (c6x_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/cr16/cr16.h (HARD_REGNO_MODE_OK): Delete.
* config/cr16/cr16-protos.h (cr16_hard_regno_mode_ok): Delete.
* config/cr16/cr16.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(cr16_hard_regno_mode_ok): Make static and return a bool.
* config/cris/cris.h (HARD_REGNO_MODE_OK): Delete.
* config/cris/cris.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(cris_hard_regno_mode_ok): New function.
* config/epiphany/epiphany.h (epiphany_hard_regno_mode_ok): Delete.
(epiphany_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/epiphany/epiphany-protos.h (hard_regno_mode_ok): Delete.
* config/epiphany/epiphany.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(hard_regno_mode_ok): Rename to...
(epiphany_hard_regno_mode_ok): ...this. Make static and return a bool.
* config/fr30/fr30.h (HARD_REGNO_MODE_OK): Delete.
* config/fr30/fr30.md: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/frv/frv.h (HARD_REGNO_MODE_OK): Delete.
* config/frv/frv-protos.h (frv_hard_regno_mode_ok): Delete.
* config/frv/frv.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(frv_hard_regno_mode_ok): Make static and return a bool.
* config/frv/frv.md: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/ft32/ft32.h (HARD_REGNO_MODE_OK): Delete.
* config/h8300/h8300.h (HARD_REGNO_MODE_OK): Delete.
* config/h8300/h8300-protos.h (h8300_hard_regno_mode_ok): Delete.
* config/h8300/h8300.c (h8300_hard_regno_mode_ok): Make static
and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/i386/i386.h (HARD_REGNO_MODE_OK): Delete.
* config/i386/i386-protos.h (ix86_hard_regno_mode_ok): Delete.
* config/i386/i386.c (ix86_hard_regno_mode_ok): Make static and
return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/ia64/ia64.h (HARD_REGNO_MODE_OK): Delete.
* config/ia64/ia64.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(ia64_hard_regno_mode_ok): New function.
* config/iq2000/iq2000.h (HARD_REGNO_MODE_OK): Delete.
* config/iq2000/iq2000.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(iq2000_hard_regno_mode_ok): New function.
* config/lm32/lm32.h (HARD_REGNO_MODE_OK): Delete.
* config/lm32/lm32.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(lm32_hard_regno_mode_ok): New function.
* config/m32c/m32c.h (HARD_REGNO_MODE_OK): Delete.
* config/m32c/m32c-protos.h (m32c_hard_regno_ok): Delete.
* config/m32c/m32c.c (class_can_hold_mode): Use m32c_hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
(m32c_hard_regno_ok): Rename to...
(m32c_hard_regno_mode_ok): ...this. Make static and return a bool.
(m32c_cannot_change_mode_class): Update accordingly.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/m32r/m32r.h (m32r_hard_regno_mode_ok): Delete.
(m32r_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/m32r/m32r.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(m32r_hard_regno_mode_ok): Rename to...
(m32r_hard_regno_modes): ...this.
(m32r_mode_class): Make static.
(m32r_hard_regno_mode_ok): New function.
* config/m68k/m68k.h (HARD_REGNO_MODE_OK): Delete.
* config/m68k/m68k-protos.h (m68k_regno_mode_ok): Delete.
* config/m68k/m68k.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(m68k_hard_regno_mode_ok): Make static.
* config/mcore/mcore.h (HARD_REGNO_MODE_OK): Delete.
* config/mcore/mcore.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(mcore_hard_regno_mode_ok): New function.
* config/microblaze/microblaze.h (microblaze_hard_regno_mode_ok)
(HARD_REGNO_MODE_OK): Delete.
* config/microblaze/microblaze.c (microblaze_hard_regno_mode_ok):
Rename to...
(microblaze_hard_regno_mode_ok_p): ...this and make static.
(microblaze_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/mips/mips.h (HARD_REGNO_MODE_OK): Delete.
(mips_hard_regno_mode_ok): Delete.
* config/mips/mips.c (mips_hard_regno_mode_ok): Rename to...
(mips_hard_regno_mode_ok_p): ...this and make static.
(mips_hard_regno_mode_ok_p): Rename to...
(mips_hard_regno_mode_ok_uncached): ...this.
(mips_hard_regno_mode_ok): New function.
(mips_class_max_nregs): Use mips_hard_regno_mode_ok instead
of HARD_REGNO_MODE_OK.
(mips_option_override): Update after above name changes.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/mmix/mmix.h (HARD_REGNO_MODE_OK): Delete.
* config/mn10300/mn10300.h (HARD_REGNO_MODE_OK): Delete.
* config/mn10300/mn10300-protos.h (mn10300_hard_regno_mode_ok): Delete.
* config/mn10300/mn10300.c (mn10300_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/moxie/moxie.h (HARD_REGNO_MODE_OK): Delete.
* config/msp430/msp430.h (HARD_REGNO_MODE_OK): Delete.
* config/msp430/msp430-protos.h (msp430_hard_regno_mode_ok): Delete.
* config/msp430/msp430.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(msp430_hard_regno_mode_ok): Make static and return a bool.
* config/nds32/nds32.h (HARD_REGNO_MODE_OK): Delete.
* config/nds32/nds32-protos.h (nds32_hard_regno_mode_ok): Delete.
* config/nds32/nds32.c (nds32_hard_regno_mode_ok): Make static
and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/nios2/nios2.h (HARD_REGNO_MODE_OK): Delete.
* config/nvptx/nvptx.h (HARD_REGNO_MODE_OK): Delete.
* config/pa/pa.h (MODES_TIEABLE_P): Update commentary.
* config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): Rename to...
(PA_HARD_REGNO_MODE_OK): ...this
* config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Rename to...
(PA_HARD_REGNO_MODE_OK): ...this.
* config/pa/pa.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(pa_hard_regno_mode_ok): New function.
* config/pdp11/pdp11.h (HARD_REGNO_MODE_OK): Delete.
* config/pdp11/pdp11.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(pdp11_hard_regno_mode_ok): New function.
* config/powerpcspe/powerpcspe.h (HARD_REGNO_MODE_OK): Delete.
* config/powerpcspe/powerpcspe-protos.h (rs6000_hard_regno_mode_ok_p):
Delete.
* config/powerpcspe/powerpcspe.c (rs6000_hard_regno_mode_ok_p):
Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(rs6000_hard_regno_mode_ok): Rename to...
(rs6000_hard_regno_mode_ok_uncached): ...this.
(rs6000_init_hard_regno_mode_ok): Update accordingly.
(rs6000_hard_regno_mode_ok): New function.
* config/riscv/riscv.h (HARD_REGNO_MODE_OK): Delete.
* config/riscv/riscv-protos.h (riscv_hard_regno_mode_ok_p): Delete.
* config/riscv/riscv.c (riscv_hard_regno_mode_ok_p): Rename to...
(riscv_hard_regno_mode_ok): ...this and make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/rl78/rl78.h (HARD_REGNO_MODE_OK): Delete.
* config/rl78/rl78-protos.h (rl78_hard_regno_mode_ok): Delete.
* config/rl78/rl78.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(rl78_hard_regno_mode_ok): Make static and return bool.
* config/rs6000/rs6000.h (HARD_REGNO_MODE_OK): Delete.
* config/rs6000/rs6000-protos.h (rs6000_hard_regno_mode_ok_p):
Delete.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok_p): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(rs6000_hard_regno_mode_ok): Rename to...
(rs6000_hard_regno_mode_ok_uncached): ...this.
(rs6000_init_hard_regno_mode_ok): Update accordingly.
(rs6000_hard_regno_mode_ok): New function.
* config/rx/rx.h (HARD_REGNO_MODE_OK): Delete.
* config/rx/rx.c (rx_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/s390/s390.h (HARD_REGNO_MODE_OK): Delete.
* config/s390/s390-protos.h (s390_hard_regno_mode_ok): Delete.
* config/s390/s390.c (s390_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/sh/sh.h (HARD_REGNO_MODE_OK): Delete.
* config/sh/sh-protos.h (sh_hard_regno_mode_ok): Delete.
* config/sh/sh.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(sh_hard_regno_mode_ok): Make static.
* config/sparc/constraints.md: Refer to targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* config/sparc/sparc.h (hard_regno_mode_classes): Delete.
(sparc_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/sparc/sparc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(hard_regno_mode_classes): Make static.
(sparc_mode_class): Likewise.
(sparc_hard_regno_mode_ok): New function.
* config/spu/spu.h (HARD_REGNO_MODE_OK): Delete.
* config/stormy16/stormy16.h (HARD_REGNO_MODE_OK): Delete.
* config/stormy16/stormy16.c (xstormy16_hard_regno_mode_ok): New
function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/tilegx/tilegx.h (HARD_REGNO_MODE_OK): Delete.
* config/tilepro/tilepro.h (HARD_REGNO_MODE_OK): Delete.
* config/v850/v850.h (HARD_REGNO_MODE_OK): Delete.
* config/v850/v850.c (v850_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/vax/vax.h (HARD_REGNO_MODE_OK): Delete.
* config/visium/visium.h (HARD_REGNO_MODE_OK): Delete.
* config/visium/visium.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(visium_hard_regno_mode_ok): New function.
* config/visium/visium.md: Refer to targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* config/xtensa/xtensa.h (xtensa_hard_regno_mode_ok): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/xtensa/xtensa.c (xtensa_hard_regno_mode_ok): Rename to...
(xtensa_hard_regno_mode_ok_p): ...this and make static.
(xtensa_option_override): Update accordingly.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(xtensa_hard_regno_mode_ok): New function.
* system.h (HARD_REGNO_MODE_OK): Poison.
2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>

2
gcc/alias.c
View File

@ -3186,7 +3186,7 @@ init_alias_target (void)
argument. FUNCTION_ARG_REGNO_P tests outgoing register
numbers, so translate if necessary due to register windows. */
if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (i))
&& HARD_REGNO_MODE_OK (i, Pmode))
&& targetm.hard_regno_mode_ok (i, Pmode))
static_reg_base_value[i] = arg_base_value;
static_reg_base_value[STACK_POINTER_REGNUM]

9
gcc/caller-save.c
View File

@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. If not see
#include "addresses.h"
#include "dumpfile.h"
#include "rtl-iter.h"
#include "target.h"
#define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD)
@ -111,11 +112,11 @@ reg_save_code (int reg, machine_mode mode)
bool ok;
if (cached_reg_save_code[reg][mode])
return cached_reg_save_code[reg][mode];
if (!HARD_REGNO_MODE_OK (reg, mode))
if (!targetm.hard_regno_mode_ok (reg, mode))
{
/* Depending on how HARD_REGNO_MODE_OK is defined, range propagation
might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert
below silences a warning. */
/* Depending on how targetm.hard_regno_mode_ok is defined, range
propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER.
So the assert below silences a warning. */
gcc_assert (reg < FIRST_PSEUDO_REGISTER);
cached_reg_save_code[reg][mode] = -1;
cached_reg_restore_code[reg][mode] = -1;

11
gcc/combine.c
View File

@ -2011,7 +2011,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
if (REG_P (src)
&& ((REGNO (dest) < FIRST_PSEUDO_REGISTER
&& ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
&& !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
/* Don't extend the life of a hard register unless it is
user variable (if we have few registers) or it can't
fit into the desired register (meaning something special
@ -2020,7 +2020,8 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
reload can't handle a conflict with constraints of other
inputs. */
|| (REGNO (src) < FIRST_PSEUDO_REGISTER
&& ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
&& !targetm.hard_regno_mode_ok (REGNO (src),
GET_MODE (src)))))
return 0;
}
else if (GET_CODE (dest) != CC0)
@ -2210,8 +2211,8 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
|| (REG_P (inner_dest)
&& REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
&& (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
GET_MODE (inner_dest))))
&& !targetm.hard_regno_mode_ok (REGNO (inner_dest),
GET_MODE (inner_dest)))
|| (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
|| (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
return 0;
@ -2454,7 +2455,7 @@ can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
/* Allow hard registers if the new mode is legal, and occupies no more
registers than the old mode. */
if (regno < FIRST_PSEUDO_REGISTER)
return (HARD_REGNO_MODE_OK (regno, mode)
return (targetm.hard_regno_mode_ok (regno, mode)
&& REG_NREGS (x) >= hard_regno_nregs[regno][mode]);
/* Or a pseudo that is only used once. */

1
gcc/config/aarch64/aarch64-protos.h
View File

@ -375,7 +375,6 @@ int aarch64_asm_preferred_eh_data_format (int, int);
int aarch64_fpconst_pow_of_2 (rtx);
machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
machine_mode);
int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
int aarch64_hard_regno_nregs (unsigned, machine_mode);
int aarch64_uxt_size (int, HOST_WIDE_INT);
int aarch64_vec_fpconst_pow_of_2 (rtx);

13
gcc/config/aarch64/aarch64.c
View File

@ -1083,9 +1083,9 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode mode)
gcc_unreachable ();
}
/* Implement HARD_REGNO_MODE_OK. */
/* Implement TARGET_HARD_REGNO_MODE_OK. */
int
static bool
aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
@ -1101,7 +1101,7 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
return mode == Pmode;
if (GP_REGNUM_P (regno) && ! aarch64_vect_struct_mode_p (mode))
return 1;
return true;
if (FP_REGNUM_P (regno))
{
@ -1109,10 +1109,10 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
return
(regno + aarch64_hard_regno_nregs (regno, mode) - 1) <= V31_REGNUM;
else
return 1;
return true;
}
return 0;
return false;
}
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
@ -15669,6 +15669,9 @@ aarch64_libgcc_floating_mode_supported_p
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
aarch64_hard_regno_call_part_clobbered

2
gcc/config/aarch64/aarch64.h
View File

@ -403,8 +403,6 @@ extern unsigned aarch64_architecture_version;
#define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
#define DWARF2_UNWIND_INFO 1

19
gcc/config/alpha/alpha.c
View File

@ -9891,6 +9891,22 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
build2 (COMPOUND_EXPR, void_type_node,
reload_fenv, restore_fnenv), update_call);
}
/* Implement TARGET_HARD_REGNO_MODE_OK. On Alpha, the integer registers
can hold any mode. The floating-point registers can hold 64-bit
integers as well, but not smaller values. */
static bool
alpha_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (IN_RANGE (regno, 32, 62))
return (mode == SFmode
|| mode == DFmode
|| mode == DImode
|| mode == SCmode
|| mode == DCmode);
return true;
}
/* Initialize the GCC target structure. */
#if TARGET_ABI_OPEN_VMS
@ -10085,6 +10101,9 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV alpha_atomic_assign_expand_fenv
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK alpha_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;

14
gcc/config/alpha/alpha.h
View File

@ -385,16 +385,6 @@ extern enum alpha_fp_trap_mode alpha_fptm;
#define HARD_REGNO_NREGS(REGNO, MODE) \
CEIL (GET_MODE_SIZE (MODE), UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On Alpha, the integer registers can hold any mode. The floating-point
registers can hold 64-bit integers as well, but not smaller values. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(IN_RANGE ((REGNO), 32, 62) \
? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \
|| (MODE) == SCmode || (MODE) == DCmode \
: 1)
/* A C expression that is nonzero if a value of mode
MODE1 is accessible in mode MODE2 without copying.
@ -402,8 +392,8 @@ extern enum alpha_fp_trap_mode alpha_fptm;
in an FP register but MODE2 could not. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(HARD_REGNO_MODE_OK (32, (MODE1)) \
? HARD_REGNO_MODE_OK (32, (MODE2)) \
(targetm.hard_regno_mode_ok (32, (MODE1)) \
? targetm.hard_regno_mode_ok (32, (MODE2)) \
: 1)
/* Specify the registers used for certain standard purposes.

27
gcc/config/arc/arc.c
View File

@ -590,6 +590,9 @@ static void arc_finalize_pic (void);
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK arc_hard_regno_mode_ok
/* Try to keep the (mov:DF _, reg) as early as possible so
that the d<add/sub/mul>h-lr insns appear together and can
use the peephole2 pattern. */
@ -1483,7 +1486,7 @@ enum arc_mode_class {
/* Value is 1 if register/mode pair is acceptable on arc. */
unsigned int arc_hard_regno_mode_ok[] = {
static unsigned int arc_hard_regno_modes[] = {
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, D_MODES,
@ -1509,7 +1512,7 @@ unsigned int arc_hard_regno_mode_ok[] = {
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES
};
unsigned int arc_mode_class [NUM_MACHINE_MODES];
static unsigned int arc_mode_class [NUM_MACHINE_MODES];
enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
@ -1730,10 +1733,10 @@ arc_conditional_register_usage (void)
CLEAR_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], LP_COUNT);
/* Instead of taking out SF_MODE like below, forbid it outright. */
arc_hard_regno_mode_ok[60] = 0;
arc_hard_regno_modes[60] = 0;
}
else
arc_hard_regno_mode_ok[60] = 1 << (int) S_MODE;
arc_hard_regno_modes[60] = 1 << (int) S_MODE;
}
/* ARCHS has 64-bit data-path which makes use of the even-odd paired
@ -1742,7 +1745,7 @@ arc_conditional_register_usage (void)
{
for (regno = 1; regno < 32; regno +=2)
{
arc_hard_regno_mode_ok[regno] = S_MODES;
arc_hard_regno_modes[regno] = S_MODES;
}
}
@ -1820,8 +1823,8 @@ arc_conditional_register_usage (void)
fixed_regs[42] = 1;
fixed_regs[43] = 1;
arc_hard_regno_mode_ok[40] = 0;
arc_hard_regno_mode_ok[42] = 0;
arc_hard_regno_modes[40] = 0;
arc_hard_regno_modes[42] = 0;
CLEAR_HARD_REG_SET(reg_class_contents [DOUBLE_REGS]);
}
@ -1867,10 +1870,18 @@ arc_conditional_register_usage (void)
fixed_regs[ACCL_REGNO] = 0;
fixed_regs[ACCH_REGNO] = 0;
arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES;
arc_hard_regno_modes[ACC_REG_FIRST] = D_MODES;
}
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
arc_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return (arc_hard_regno_modes[regno] & arc_mode_class[mode]) != 0;
}
/* Handle an "interrupt" attribute; arguments as in
struct attribute_spec.handler. */

12
gcc/config/arc/arc.h
View File

@ -450,19 +450,13 @@ if (GET_MODE_CLASS (MODE) == MODE_INT \
&& REGNO >= ARC_FIRST_SIMD_VR_REG && REGNO <= ARC_LAST_SIMD_VR_REG) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
extern unsigned int arc_hard_regno_mode_ok[];
extern unsigned int arc_mode_class[];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
MODE2)' must be zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `TARGET_MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Tie QI/HI/SI modes together. */
#define MODES_TIEABLE_P(MODE1, MODE2) \

1
gcc/config/arm/arm-protos.h
View File

@ -61,7 +61,6 @@ extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
rtx label_ref);
extern bool arm_vector_mode_supported_p (machine_mode);
extern bool arm_small_register_classes_for_mode_p (machine_mode);
extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool arm_modes_tieable_p (machine_mode, machine_mode);
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);

16
gcc/config/arm/arm.c
View File

@ -313,6 +313,7 @@ static unsigned int arm_elf_section_type_flags (tree decl, const char *name,
int reloc);
static void arm_expand_divmod_libfunc (rtx, machine_mode, rtx, rtx, rtx *, rtx *);
static opt_scalar_float_mode arm_floatn_mode (int, bool);
static bool arm_hard_regno_mode_ok (unsigned int, machine_mode);
/* Table of machine attributes. */
static const struct attribute_spec arm_attribute_table[] =
@ -780,6 +781,8 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_FIXED_CONDITION_CODE_REGS
#define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK arm_hard_regno_mode_ok
/* Obstack for minipool constant handling. */
static struct obstack minipool_obstack;
@ -23344,9 +23347,8 @@ thumb2_asm_output_opcode (FILE * stream)
}
}
/* Returns true if REGNO is a valid register
for holding a quantity of type MODE. */
int
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
@ -23390,7 +23392,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
|| (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
|| (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
return FALSE;
return false;
}
if (TARGET_REALLY_IWMMXT)
@ -23409,10 +23411,10 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
if (regno <= LAST_ARM_REGNUM)
{
if (ARM_NUM_REGS (mode) > 4)
return FALSE;
return false;
if (TARGET_THUMB2)
return TRUE;
return true;
return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
}
@ -23422,7 +23424,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
return FALSE;
return false;
}
/* Implement MODES_TIEABLE_P. */

4
gcc/config/arm/arm.h
View File

@ -990,10 +990,6 @@ extern int arm_arch_cmse;
&& !IS_VFP_REGNUM (REGNO) \
? 1 : ARM_NUM_REGS (MODE))
/* Return true if REGNO is suitable for holding a quantity of type MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
arm_hard_regno_mode_ok ((REGNO), (MODE))
#define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
#define VALID_IWMMXT_REG_MODE(MODE) \

4
gcc/config/arm/arm.md
View File

@ -5804,7 +5804,7 @@
operands[1] = force_reg (DImode, operands[1]);
}
if (REG_P (operands[0]) && REGNO (operands[0]) <= LAST_ARM_REGNUM
&& !HARD_REGNO_MODE_OK (REGNO (operands[0]), DImode))
&& !targetm.hard_regno_mode_ok (REGNO (operands[0]), DImode))
{
/* Avoid LDRD's into an odd-numbered register pair in ARM state
when expanding function calls. */
@ -5823,7 +5823,7 @@
DONE;
}
else if (REG_P (operands[1]) && REGNO (operands[1]) <= LAST_ARM_REGNUM
&& !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode))
&& !targetm.hard_regno_mode_ok (REGNO (operands[1]), DImode))
{
/* Avoid STRD's from an odd-numbered register pair in ARM state
when expanding function prologue. */

1
gcc/config/avr/avr-protos.h
View File

@ -111,7 +111,6 @@ extern int avr_jump_mode (rtx x, rtx_insn *insn);
extern int test_hard_reg_class (enum reg_class rclass, rtx x);
extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest);
extern int avr_hard_regno_mode_ok (int regno, machine_mode mode);
extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand,
int num_operands);
extern int avr_simplify_comparison_p (machine_mode mode,

18
gcc/config/avr/avr.c
View File

@ -12149,14 +12149,12 @@ jump_over_one_insn_p (rtx_insn *insn, rtx dest)
}
/* Worker function for `HARD_REGNO_MODE_OK'. */
/* Returns 1 if a value of mode MODE can be stored starting with hard
register number REGNO. On the enhanced core, anything larger than
1 byte must start in even numbered register for "movw" to work
(this way we don't have to check for odd registers everywhere). */
/* Implement TARGET_HARD_REGNO_MODE_OK. On the enhanced core, anything
larger than 1 byte must start in even numbered register for "movw" to
work (this way we don't have to check for odd registers everywhere). */
int
avr_hard_regno_mode_ok (int regno, machine_mode mode)
static bool
avr_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* NOTE: 8-bit values must not be disallowed for R28 or R29.
Disallowing QI et al. in these regs might lead to code like
@ -12169,7 +12167,7 @@ avr_hard_regno_mode_ok (int regno, machine_mode mode)
/* Any GENERAL_REGS register can hold 8-bit values. */
if (GET_MODE_SIZE (mode) == 1)
return 1;
return true;
/* FIXME: Ideally, the following test is not needed.
However, it turned out that it can reduce the number
@ -12178,7 +12176,7 @@ avr_hard_regno_mode_ok (int regno, machine_mode mode)
if (GET_MODE_SIZE (mode) >= 4
&& regno >= REG_X)
return 0;
return false;
/* All modes larger than 8 bits should start in an even register. */
@ -14691,6 +14689,8 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg,
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE avr_conditional_register_usage
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK avr_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK avr_hard_regno_scratch_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED

2
gcc/config/avr/avr.h
View File

@ -212,8 +212,6 @@ FIXME: DRIVER_SELF_SPECS has changed.
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) 1
enum reg_class {

1
gcc/config/bfin/bfin-protos.h
View File

@ -71,7 +71,6 @@ extern char *bfin_asm_long (void);
extern char *bfin_asm_short (void);
extern int log2constp (unsigned HOST_WIDE_INT);
extern int hard_regno_mode_ok (int, machine_mode);
extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
extern HOST_WIDE_INT bfin_initial_elimination_offset (int, int);

15
gcc/config/bfin/bfin.c
View File

@ -2114,16 +2114,18 @@ bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
CALL_INSN_FUNCTION_USAGE (call) = use;
}
/* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
/* Implement TARGET_HARD_REGNO_MODE_OK.
int
hard_regno_mode_ok (int regno, machine_mode mode)
Do not allow to store a value in REG_CC for any mode.
Do not allow to store value in pregs if mode is not SI. */
static bool
bfin_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Allow only dregs to store value of mode HI or QI */
enum reg_class rclass = REGNO_REG_CLASS (regno);
if (mode == CCmode)
return 0;
return false;
if (mode == V2HImode)
return D_REGNO_P (regno);
@ -2139,7 +2141,7 @@ hard_regno_mode_ok (int regno, machine_mode mode)
if (mode == SImode
&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
return 1;
return true;
return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
}
@ -5845,4 +5847,7 @@ bfin_conditional_register_usage (void)
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P bfin_can_use_doloop_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK bfin_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;

10
gcc/config/bfin/bfin.h
View File

@ -677,10 +677,6 @@ enum reg_class
registers. */
#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
/* Do not allow to store a value in REG_CC for any mode */
/* Do not allow to store value in pregs if mode is not SI*/
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
@ -700,9 +696,9 @@ enum reg_class
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
MODE2)' must be zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| ((GET_MODE_CLASS (MODE1) == MODE_INT \

2
gcc/config/bfin/predicates.md
View File

@ -79,7 +79,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
if (REGNO (op) < FIRST_PSEUDO_REGISTER)
return HARD_REGNO_MODE_OK (REGNO (op), mode);
return targetm.hard_regno_mode_ok (REGNO (op), mode);
return 1;
})

11
gcc/config/c6x/c6x.c
View File

@ -6696,6 +6696,14 @@ c6x_debug_unwind_info (void)
return default_debug_unwind_info ();
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
c6x_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD || (regno & 1) == 0;
}
/* Target Structure. */
@ -6862,6 +6870,9 @@ c6x_debug_unwind_info (void)
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL c6x_builtin_decl
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK c6x_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-c6x.h"

3
gcc/config/c6x/c6x.h
View File

@ -185,9 +185,6 @@ extern c6x_cpu_t c6x_arch;
((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \
/ UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \
? 1 : ((reg) & 1) == 0)
#define MODES_TIEABLE_P(mode1, mode2) \
((mode1) == (mode2) || \
(GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \

1
gcc/config/cr16/cr16-protos.h
View File

@ -23,7 +23,6 @@
/* Register usage. */
extern enum reg_class cr16_regno_reg_class (int);
extern int cr16_hard_regno_mode_ok (int regno, machine_mode);
/* Passing function arguments. */
extern int cr16_function_arg_regno_p (int);

24
gcc/config/cr16/cr16.c
View File

@ -220,6 +220,9 @@ static const struct attribute_spec cr16_attribute_table[] = {
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK cr16_hard_regno_mode_ok
/* Target hook implementations. */
/* Implements hook TARGET_RETURN_IN_MEMORY. */
@ -463,28 +466,31 @@ cr16_regno_reg_class (int regno)
return NO_REGS;
}
/* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
int
cr16_hard_regno_mode_ok (int regno, machine_mode mode)
/* Implement TARGET_HARD_REGNO_MODE_OK. On the CR16 architecture, all
registers can hold all modes, except that double precision floats
(and double ints) must fall on even-register boundaries. */
static bool
cr16_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if ((GET_MODE_SIZE (mode) >= 4) && (regno == 11))
return 0;
return false;
if (mode == DImode || mode == DFmode)
{
if ((regno > 8) || (regno & 1))
return 0;
return 1;
return false;
return true;
}
if ((TARGET_INT32)
&& ((regno >= 12) && (GET_MODE_SIZE (mode) < 4 )))
return 0;
return false;
/* CC can only hold CCmode values. */
if (GET_MODE_CLASS (mode) == MODE_CC)
return 0;
return 1;
return false;
return true;
}
/* Returns register number for function return value.*/

7
gcc/config/cr16/cr16.h
View File

@ -204,13 +204,6 @@ while (0)
? ((GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD)\
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Nonzero if it is permissible to store a value of mode @var{mode} in hard
register number @var{regno} (or in several registers starting with that
one). On the CR16 architecture, all registers can hold all modes,
except that double precision floats (and double ints) must fall on
even-register boundaries. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) cr16_hard_regno_mode_ok (REGNO, MODE)
#define NOTICE_UPDATE_CC(EXP, INSN) \
notice_update_cc ((EXP))

16
gcc/config/cris/cris.c
View File

@ -163,6 +163,7 @@ static rtx cris_function_value(const_tree, const_tree, bool);
static rtx cris_libcall_value (machine_mode, const_rtx);
static bool cris_function_value_regno_p (const unsigned int);
static void cris_file_end (void);
static bool cris_hard_regno_mode_ok (unsigned int, machine_mode);
/* This is the parsed result of the "-max-stack-stackframe=" option. If
it (still) is zero, then there was no such option given. */
@ -280,6 +281,9 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
#undef TARGET_FUNCTION_VALUE_REGNO_P
#define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Helper for cris_load_multiple_op and cris_ret_movem_op. */
@ -4292,6 +4296,18 @@ cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
sake of a trampoline. */
}
/* Implement TARGET_HARD_REGNO_MODE_OK.
CRIS permits all registers to hold all modes. Well, except for the
condition-code register. And we can't hold larger-than-register size
modes in the last special register that can hold a full 32 bits. */
static bool
cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return ((mode == CCmode || regno != CRIS_CC0_REGNUM)
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM)));
}
#if 0
/* Various small functions to replace macros. Only called from a

11
gcc/config/cris/cris.h
View File

@ -477,18 +477,9 @@ extern int cris_cpu_version;
(MODE == VOIDmode \
? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* CRIS permits all registers to hold all modes. Well, except for the
condition-code register. And we can't hold larger-than-register size
modes in the last special register that can hold a full 32 bits. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(((MODE) == CCmode \
|| (REGNO) != CRIS_CC0_REGNUM) \
&& (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|| ((REGNO) != CRIS_MOF_REGNUM && (REGNO) != CRIS_ACR_REGNUM)))
/* Because CCmode isn't covered by the "narrower mode" statement in
tm.texi, we can still say all modes are tieable despite not having an
always 1 HARD_REGNO_MODE_OK. */
always 1 TARGET_HARD_REGNO_MODE_OK. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1

1
gcc/config/epiphany/epiphany-protos.h
View File

@ -38,7 +38,6 @@ extern void epiphany_expand_prologue (void);
extern void epiphany_expand_epilogue (int);
extern int epiphany_initial_elimination_offset (int, int);
extern void epiphany_init_expanders (void);
extern int hard_regno_mode_ok (int regno, machine_mode mode);
#ifdef HARD_CONST
extern void emit_set_fp_mode (int entity, int mode, int prev_mode,
HARD_REG_SET regs_live);

12
gcc/config/epiphany/epiphany.c
View File

@ -170,6 +170,9 @@ static rtx_insn *frame_insn (rtx);
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK epiphany_hard_regno_mode_ok
bool
epiphany_is_interrupt_p (tree decl)
@ -355,14 +358,15 @@ get_epiphany_condition_code (rtx comparison)
}
/* Return 1 if hard register REGNO can hold a value of machine_mode MODE. */
int
hard_regno_mode_ok (int regno, machine_mode mode)
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
epiphany_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return (regno & 1) == 0 && GPR_P (regno);
else
return 1;
return true;
}
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,

11
gcc/config/epiphany/epiphany.h
View File

@ -309,18 +309,13 @@ along with GCC; see the file COPYING3. If not see
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
extern const unsigned int epiphany_hard_regno_mode_ok[];
extern unsigned int epiphany_mode_class[];
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
MODE2)' must be zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1

12
gcc/config/fr30/fr30.h
View File

@ -246,19 +246,13 @@ along with GCC; see the file COPYING3. If not see
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
MODE in hard register number REGNO (or in several registers starting with
that one). */
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/*}}}*/

19
gcc/config/fr30/fr30.md
View File

@ -118,9 +118,9 @@
;; patterns `reload_inM' or `reload_outM' to handle them.
;; The constraints on a `moveM' must permit moving any hard register to any
;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
;; value of 2.
;; other hard register provided that `TARGET_HARD_REGNO_MODE_OK' permits mode
;; M in both registers and `REGISTER_MOVE_COST' applied to their classes
;; returns a value of 2.
;; It is obligatory to support floating point `moveM' instructions
;; into and out of any registers that can hold fixed point values,
@ -128,12 +128,13 @@
;; `DImode') can be in those registers and they may have floating
;; point members.
;; There may also be a need to support fixed point `moveM' instructions in and
;; out of floating point registers. Unfortunately, I have forgotten why this
;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
;; rejects fixed point values in floating point registers, then the constraints
;; of the fixed point `moveM' instructions must be designed to avoid ever
;; trying to reload into a floating point register.
;; There may also be a need to support fixed point `moveM' instructions
;; in and out of floating point registers. Unfortunately, I have
;; forgotten why this was so, and I don't know whether it is still true.
;; If `TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in floating
;; point registers, then the constraints of the fixed point `moveM'
;; instructions must be designed to avoid ever trying to reload into a
;; floating point register.
;;}}}
;;{{{ Push and Pop

1
gcc/config/frv/frv-protos.h
View File

@ -74,7 +74,6 @@ extern void frv_ifcvt_modify_cancel (struct ce_if_block *);
extern enum reg_class frv_secondary_reload_class
(enum reg_class,
machine_mode, rtx);
extern int frv_hard_regno_mode_ok (int, machine_mode);
extern int frv_hard_regno_nregs (int, machine_mode);
extern int frv_class_max_nregs (enum reg_class rclass,
machine_mode mode);

68
gcc/config/frv/frv.c
View File

@ -399,6 +399,7 @@ static bool frv_can_eliminate (const int, const int);
static void frv_conditional_register_usage (void);
static void frv_trampoline_init (rtx, tree, rtx);
static bool frv_class_likely_spilled_p (reg_class_t);
static bool frv_hard_regno_mode_ok (unsigned int, machine_mode);
/* Initialize the GCC target structure. */
#undef TARGET_PRINT_OPERAND
@ -516,6 +517,9 @@ static bool frv_class_likely_spilled_p (reg_class_t);
#undef TARGET_LIBCALL_VALUE
#define TARGET_LIBCALL_VALUE frv_libcall_value
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
#define FRV_SYMBOL_REF_TLS_P(RTX) \
@ -6517,62 +6521,10 @@ frv_adjust_field_align (tree field, int computed)
}
/* A C expression that is nonzero if it is permissible to store a value of mode
MODE in hard register number REGNO (or in several registers starting with
that one). For a machine where all registers are equivalent, a suitable
definition is
/* Implement TARGET_HARD_REGNO_MODE_OK. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
It is not necessary for this macro to check for the numbers of fixed
registers, because the allocation mechanism considers them to be always
occupied.
On some machines, double-precision values must be kept in even/odd register
pairs. The way to implement that is to define this macro to reject odd
register numbers for such modes.
The minimum requirement for a mode to be OK in a register is that the
`movMODE' instruction pattern support moves between the register and any
other hard register for which the mode is OK; and that moving a value into
the register and back out not alter it.
Since the same instruction used to move `SImode' will work for all narrower
integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
to distinguish between these modes, provided you define patterns `movhi',
etc., to take advantage of this. This is useful because of the interaction
between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
all integer modes to be tieable.
Many machines have special registers for floating point arithmetic. Often
people assume that floating point machine modes are allowed only in floating
point registers. This is not true. Any registers that can hold integers
can safely *hold* a floating point machine mode, whether or not floating
arithmetic can be done on it in those registers. Integer move instructions
can be used to move the values.
On some machines, though, the converse is true: fixed-point machine modes
may not go in floating registers. This is true if the floating registers
normalize any value stored in them, because storing a non-floating value
there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
fixed-point machine modes in floating registers. But if the floating
registers do not automatically normalize, if you can store any bit pattern
in one and retrieve it unchanged without a trap, then any machine mode may
go in a floating register, so you can define this macro to say so.
The primary significance of special floating registers is rather that they
are the registers acceptable in floating point arithmetic instructions.
However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
writing the proper constraints for those instructions.
On some machines, the floating registers are especially slow to access, so
that it is better to store a value in a stack frame than in such a register
if floating point arithmetic is not being done. As long as the floating
registers are not in class `GENERAL_REGS', they will not be used unless some
pattern's constraint asks for one. */
int
frv_hard_regno_mode_ok (int regno, machine_mode mode)
static bool
frv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
int base;
int mask;
@ -6624,18 +6576,18 @@ frv_hard_regno_mode_ok (int regno, machine_mode mode)
/* Fill in the table. */
else
return 0;
return false;
/* Anything smaller than an SI is OK in any word-sized register. */
if (GET_MODE_SIZE (mode) < 4)
return 1;
return true;
mask = (GET_MODE_SIZE (mode) / 4) - 1;
}
return (((regno - base) & mask) == 0);
}
return 0;
return false;
}

61
gcc/config/frv/frv.h
View File

@ -763,68 +763,13 @@
we can build the appropriate instructions to properly reload the values. */
#define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
/* A C expression that is nonzero if it is permissible to store a value of mode
MODE in hard register number REGNO (or in several registers starting with
that one). For a machine where all registers are equivalent, a suitable
definition is
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
It is not necessary for this macro to check for the numbers of fixed
registers, because the allocation mechanism considers them to be always
occupied.
On some machines, double-precision values must be kept in even/odd register
pairs. The way to implement that is to define this macro to reject odd
register numbers for such modes.
The minimum requirement for a mode to be OK in a register is that the
`movMODE' instruction pattern support moves between the register and any
other hard register for which the mode is OK; and that moving a value into
the register and back out not alter it.
Since the same instruction used to move `SImode' will work for all narrower
integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
to distinguish between these modes, provided you define patterns `movhi',
etc., to take advantage of this. This is useful because of the interaction
between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
all integer modes to be tieable.
Many machines have special registers for floating point arithmetic. Often
people assume that floating point machine modes are allowed only in floating
point registers. This is not true. Any registers that can hold integers
can safely *hold* a floating point machine mode, whether or not floating
arithmetic can be done on it in those registers. Integer move instructions
can be used to move the values.
On some machines, though, the converse is true: fixed-point machine modes
may not go in floating registers. This is true if the floating registers
normalize any value stored in them, because storing a non-floating value
there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
fixed-point machine modes in floating registers. But if the floating
registers do not automatically normalize, if you can store any bit pattern
in one and retrieve it unchanged without a trap, then any machine mode may
go in a floating register, so you can define this macro to say so.
The primary significance of special floating registers is rather that they
are the registers acceptable in floating point arithmetic instructions.
However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
writing the proper constraints for those instructions.
On some machines, the floating registers are especially slow to access, so
that it is better to store a value in a stack frame than in such a register
if floating point arithmetic is not being done. As long as the floating
registers are not in class `GENERAL_REGS', they will not be used unless some
pattern's constraint asks for one. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
/* Define this macro if the compiler should avoid copies to/from CCmode

19
gcc/config/frv/frv.md
View File

@ -1335,9 +1335,9 @@
;; patterns `reload_inM' or `reload_outM' to handle them.
;; The constraints on a `moveM' must permit moving any hard register to any
;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
;; value of 2.
;; other hard register provided that `TARGET_HARD_REGNO_MODE_OK' permits
;; mode M in both registers and `REGISTER_MOVE_COST' applied to their
;; classes returns a value of 2.
;; It is obligatory to support floating point `moveM' instructions
;; into and out of any registers that can hold fixed point values,
@ -1345,12 +1345,13 @@
;; `DImode') can be in those registers and they may have floating
;; point members.
;; There may also be a need to support fixed point `moveM' instructions in and
;; out of floating point registers. Unfortunately, I have forgotten why this
;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
;; rejects fixed point values in floating point registers, then the constraints
;; of the fixed point `moveM' instructions must be designed to avoid ever
;; trying to reload into a floating point register.
;; There may also be a need to support fixed point `moveM' instructions
;; in and out of floating point registers. Unfortunately, I have
;; forgotten why this was so, and I don't know whether it is still true.
;; If `TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in floating
;; point registers, then the constraints of the fixed point `moveM'
;; instructions must be designed to avoid ever trying to reload into a
;; floating point register.
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")

6
gcc/config/ft32/ft32.h
View File

@ -166,12 +166,6 @@ enum reg_class
/* We can't copy to or from our CC register. */
#define AVOID_CCMODE_COPIES 1
/* A C expression that is nonzero if it is permissible to store a
value of mode MODE in hard register number REGNO (or in several
registers starting with that one). All gstore registers are
equivalent, so we can set this to 1. */
#define HARD_REGNO_MODE_OK(R,M) 1
/* A C expression whose value is a register class containing hard
register REGNO. */
#define REGNO_REG_CLASS(R) ((R < FT32_PC) ? GENERAL_REGS : \

1
gcc/config/h8300/h8300-protos.h
View File

@ -100,7 +100,6 @@ extern int h8300_initial_elimination_offset (int, int);
extern int h8300_regs_ok_for_stm (int, rtx[]);
extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int);
extern int h8300_hard_regno_nregs (int, machine_mode);
extern int h8300_hard_regno_mode_ok (int, machine_mode);
extern bool h8300_move_ok (rtx, rtx);
struct cpp_reader;

9
gcc/config/h8300/h8300.c
View File

@ -5889,10 +5889,10 @@ h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}
/* Worker function for HARD_REGNO_MODE_OK. */
/* Implement TARGET_HARD_REGNO_MODE_OK. */
int
h8300_hard_regno_mode_ok (int regno, machine_mode mode)
static bool
h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (TARGET_H8300)
/* If an even reg, then anything goes. Otherwise the mode must be
@ -6101,6 +6101,9 @@ h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
#undef TARGET_LRA_P
#define TARGET_LRA_P hook_bool_void_false

7
gcc/config/h8300/h8300.h
View File

@ -239,13 +239,10 @@ extern const char * const *h8_reg_names;
#define HARD_REGNO_NREGS(REGNO, MODE) \
h8300_hard_regno_nregs ((REGNO), (MODE))
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
h8300_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| (((MODE1) == QImode || (MODE1) == HImode \

1
gcc/config/i386/i386-protos.h
View File

@ -167,7 +167,6 @@ extern int ix86_reg_parm_stack_space (const_tree);
extern void ix86_split_fp_branch (enum rtx_code code, rtx, rtx,
rtx, rtx, rtx);
extern bool ix86_hard_regno_mode_ok (int, machine_mode);
extern bool ix86_modes_tieable_p (machine_mode, machine_mode);
extern bool ix86_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode, int);

10
gcc/config/i386/i386.c
View File

@ -41296,11 +41296,10 @@ ix86_register_move_cost (machine_mode mode, reg_class_t class1_i,
return 2;
}
/* Return TRUE if hard register REGNO can hold a value of machine-mode
MODE. */
/* Implement TARGET_HARD_REGNO_MODE_OK. */
bool
ix86_hard_regno_mode_ok (int regno, machine_mode mode)
static bool
ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Flags and only flags can only hold CCmode values. */
if (CC_REGNO_P (regno))
@ -53261,6 +53260,9 @@ ix86_run_selftests (void)
#undef TARGET_NOCE_CONVERSION_PROFITABLE_P
#define TARGET_NOCE_CONVERSION_PROFITABLE_P ix86_noce_conversion_profitable_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK ix86_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
ix86_hard_regno_call_part_clobbered

9
gcc/config/i386/i386.h
View File

@ -1181,15 +1181,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
|| (MODE) == V8SFmode || (MODE) == V4DFmode))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
ix86_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
ix86_modes_tieable_p ((MODE1), (MODE2))

30
gcc/config/ia64/ia64.c
View File

@ -335,6 +335,8 @@ static section * ia64_hpux_function_section (tree, enum node_frequency,
static bool ia64_vectorize_vec_perm_const_ok (machine_mode vmode,
const unsigned char *sel);
static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode);
#define MAX_VECT_LEN 8
struct expand_vec_perm_d
@ -653,6 +655,9 @@ static const struct attribute_spec ia64_attribute_table[] =
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 0
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK ia64_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
@ -4251,6 +4256,31 @@ ia64_hard_regno_rename_ok (int from, int to)
return 1;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
ia64_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (FR_REGNO_P (regno))
return (GET_MODE_CLASS (mode) != MODE_CC
&& mode != BImode
&& mode != TFmode);
if (PR_REGNO_P (regno))
return mode == BImode || GET_MODE_CLASS (mode) == MODE_CC;
if (GR_REGNO_P (regno))
return mode != XFmode && mode != XCmode && mode != RFmode;
if (AR_REGNO_P (regno))
return mode == DImode;
if (BR_REGNO_P (regno))
return mode == DImode;
return false;
}
/* Target hook for assembling integer objects. Handle word-sized
aligned objects and detect the cases when @fptr is needed. */

23
gcc/config/ia64/ia64.h
View File

@ -614,30 +614,13 @@ while (0)
: FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
MODE in hard register number REGNO (or in several registers starting with
that one). */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_REGNO_P (REGNO) ? \
GET_MODE_CLASS (MODE) != MODE_CC && \
(MODE) != BImode && \
(MODE) != TFmode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? \
(MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Don't tie integer and FP modes, as that causes us to get integer registers
allocated for FP instructions. XFmode only supported in FP registers so
we can't tie it with any other modes. */

14
gcc/config/iq2000/iq2000.c
View File

@ -177,6 +177,7 @@ static rtx iq2000_libcall_value (machine_mode, const_rtx);
static void iq2000_print_operand (FILE *, rtx, int);
static void iq2000_print_operand_address (FILE *, machine_mode, rtx);
static bool iq2000_print_operand_punct_valid_p (unsigned char code);
static bool iq2000_hard_regno_mode_ok (unsigned int, machine_mode);
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS iq2000_init_builtins
@ -254,6 +255,9 @@ static bool iq2000_print_operand_punct_valid_p (unsigned char code);
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT iq2000_trampoline_init
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK iq2000_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Return nonzero if we split the address into high and low parts. */
@ -3485,4 +3489,14 @@ iq2000_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
emit_move_insn (mem, chain_value);
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
iq2000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return (REGNO_REG_CLASS (regno) == GR_REGS
? (regno & 1) == 0 || GET_MODE_SIZE (mode) <= 4
: (regno & 1) == 0 || GET_MODE_SIZE (mode) == 4);
}
#include "gt-iq2000.h"

5
gcc/config/iq2000/iq2000.h
View File

@ -165,11 +165,6 @@
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO_REG_CLASS (REGNO) == GR_REGS) \
? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
: ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \

11
gcc/config/lm32/lm32.c
View File

@ -77,6 +77,7 @@ static rtx lm32_function_arg (cumulative_args_t cum,
static void lm32_function_arg_advance (cumulative_args_t cum,
machine_mode mode,
const_tree type, bool named);
static bool lm32_hard_regno_mode_ok (unsigned int, machine_mode);
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE lm32_option_override
@ -106,6 +107,8 @@ static void lm32_function_arg_advance (cumulative_args_t cum,
#define TARGET_LRA_P hook_bool_void_false
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P lm32_legitimate_address_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK lm32_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
@ -1221,3 +1224,11 @@ lm32_move_ok (machine_mode mode, rtx operands[2]) {
return register_or_zero_operand (operands[1], mode);
return true;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
lm32_hard_regno_mode_ok (unsigned int regno, machine_mode)
{
return G_REG_P (regno);
}

2
gcc/config/lm32/lm32.h
View File

@ -166,8 +166,6 @@ do { \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) G_REG_P(REGNO)
#define MODES_TIEABLE_P(MODE1, MODE2) \
( GET_MODE_CLASS (MODE1) == MODE_INT \
&& GET_MODE_CLASS (MODE2) == MODE_INT \

1
gcc/config/m32c/m32c-protos.h
View File

@ -50,7 +50,6 @@ void m32c_expand_neg_mulpsi3 (rtx *);
int m32c_expand_setmemhi (rtx *);
bool m32c_matches_constraint_p (rtx, int);
int m32c_hard_regno_nregs (int, machine_mode);
int m32c_hard_regno_ok (int, machine_mode);
bool m32c_illegal_subreg_p (rtx);
bool m32c_immd_dbl_mov (rtx *, machine_mode);
rtx m32c_incoming_return_addr_rtx (void);

15
gcc/config/m32c/m32c.c
View File

@ -92,6 +92,8 @@ static rtx m32c_libcall_value (machine_mode, const_rtx);
/* Returns true if an address is specified, else false. */
static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
static bool m32c_hard_regno_mode_ok (unsigned int, machine_mode);
#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
#define streq(a,b) (strcmp ((a), (b)) == 0)
@ -370,7 +372,7 @@ class_can_hold_mode (reg_class_t rclass, machine_mode mode)
results[rclass][mode] = 1;
for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
if (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)
&& HARD_REGNO_MODE_OK (r, mode))
&& m32c_hard_regno_mode_ok (r, mode))
{
results[rclass][mode] = 2;
break;
@ -573,10 +575,10 @@ m32c_hard_regno_nregs (int regno, machine_mode mode)
return rv ? rv : 1;
}
/* Implements HARD_REGNO_MODE_OK. The above function does the work
/* Implement TARGET_HARD_REGNO_MODE_OK. The above function does the work
already; just test its return value. */
int
m32c_hard_regno_ok (int regno, machine_mode mode)
static bool
m32c_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return m32c_hard_regno_nregs_1 (regno, mode) != 0;
}
@ -815,7 +817,7 @@ m32c_cannot_change_mode_class (machine_mode from,
can't allow the change. */
for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
if (class_contents[rclass][0] & (1 << rn))
if (! m32c_hard_regno_ok (rn, to))
if (! m32c_hard_regno_mode_ok (rn, to))
return 1;
if (to == QImode)
@ -4487,6 +4489,9 @@ m32c_output_compare (rtx_insn *insn, rtx *operands)
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK m32c_hard_regno_mode_ok
/* The Global `targetm' Variable. */
struct gcc_target targetm = TARGET_INITIALIZER;

1
gcc/config/m32c/m32c.h
View File

@ -256,7 +256,6 @@ machine_function;
/* How Values Fit in Registers */
#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
#define AVOID_CCMODE_COPIES

16
gcc/config/m32r/m32r.c
View File

@ -102,6 +102,7 @@ static void m32r_conditional_register_usage (void);
static void m32r_trampoline_init (rtx, tree, rtx);
static bool m32r_legitimate_constant_p (machine_mode, rtx);
static bool m32r_attribute_identifier (const_tree);
static bool m32r_hard_regno_mode_ok (unsigned int, machine_mode);
/* M32R specific attributes. */
@ -209,6 +210,9 @@ static const struct attribute_spec m32r_attribute_table[] =
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK m32r_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Called by m32r_option_override to initialize various things. */
@ -270,14 +274,14 @@ enum m32r_mode_class
/* Value is 1 if register/mode pair is acceptable on arc. */
const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
static const unsigned int m32r_hard_regno_modes[FIRST_PSEUDO_REGISTER] =
{
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, C_MODES, A_MODES, A_MODES
};
unsigned int m32r_mode_class [NUM_MACHINE_MODES];
static unsigned int m32r_mode_class [NUM_MACHINE_MODES];
enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
@ -2747,6 +2751,14 @@ m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
}
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
m32r_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return (m32r_hard_regno_modes[regno] & m32r_mode_class[mode]) != 0;
}
/* Return true if using NEW_REG in place of OLD_REG is ok. */
int

12
gcc/config/m32r/m32r.h
View File

@ -396,19 +396,13 @@
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
extern unsigned int m32r_mode_class[];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
MODE2)' must be zero. */
If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
`TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Tie QI/HI/SI modes together. */
#define MODES_TIEABLE_P(MODE1, MODE2) \

1
gcc/config/m68k/m68k-protos.h
View File

@ -86,7 +86,6 @@ extern enum attr_op_mem m68k_sched_attr_op_mem (rtx_insn *);
#endif /* RTX_CODE */
extern bool m68k_regno_mode_ok (int, machine_mode);
extern enum reg_class m68k_secondary_reload_class (enum reg_class,
machine_mode, rtx);
extern enum reg_class m68k_preferred_reload_class (rtx, enum reg_class);

14
gcc/config/m68k/m68k.c
View File

@ -187,6 +187,7 @@ static bool m68k_output_addr_const_extra (FILE *, rtx);
static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
static enum flt_eval_method
m68k_excess_precision (enum excess_precision_type);
static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode);
/* Initialize the GCC target structure. */
@ -334,6 +335,9 @@ m68k_excess_precision (enum excess_precision_type);
#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
@ -5170,12 +5174,12 @@ m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
return 1;
}
/* Value is true if hard register REGNO can hold a value of machine-mode
MODE. On the 68000, we let the cpu registers can hold any mode, but
restrict the 68881 registers to floating-point modes. */
/* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
registers can hold any mode, but restrict the 68881 registers to
floating-point modes. */
bool
m68k_regno_mode_ok (int regno, machine_mode mode)
static bool
m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (DATA_REGNO_P (regno))
{

3
gcc/config/m68k/m68k.h
View File

@ -394,9 +394,6 @@ along with GCC; see the file COPYING3. If not see
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
m68k_regno_mode_ok ((REGNO), (MODE))
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
m68k_secondary_reload_class (CLASS, MODE, X)

15
gcc/config/mcore/mcore.c
View File

@ -144,6 +144,7 @@ static void mcore_option_override (void);
static bool mcore_legitimate_constant_p (machine_mode, rtx);
static bool mcore_legitimate_address_p (machine_mode, rtx, bool,
addr_space_t);
static bool mcore_hard_regno_mode_ok (unsigned int, machine_mode);
/* MCore specific attributes. */
@ -240,6 +241,9 @@ static const struct attribute_spec mcore_attribute_table[] =
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK mcore_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Adjust the stack and return the number of bytes taken to do it. */
@ -3260,3 +3264,14 @@ mcore_legitimate_address_p (machine_mode mode, rtx x, bool strict_p,
return false;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. We may keep double values in
even registers. */
static bool
mcore_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (TARGET_8ALIGN && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return (regno & 1) == 0;
return regno < 18;
}

9
gcc/config/mcore/mcore.h
View File

@ -248,15 +248,10 @@ extern char * mcore_current_function_name;
#define HARD_REGNO_NREGS(REGNO, MODE) \
(((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
We may keep double values in even registers. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))

23
gcc/config/microblaze/microblaze.c
View File

@ -176,8 +176,8 @@ REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
/* Array giving truth value on whether or not a given hard register
can support a given mode. */
char microblaze_hard_regno_mode_ok[(int)MAX_MACHINE_MODE]
[FIRST_PSEUDO_REGISTER];
static char microblaze_hard_regno_mode_ok_p[(int)MAX_MACHINE_MODE]
[FIRST_PSEUDO_REGISTER];
/* Current frame information calculated by compute_frame_size. */
struct microblaze_frame_info current_frame_info;
@ -1841,11 +1841,25 @@ microblaze_option_override (void)
else
ok = 0;
microblaze_hard_regno_mode_ok[(int) mode][regno] = ok;
microblaze_hard_regno_mode_ok_p[(int) mode][regno] = ok;
}
}
}
/* Implement TARGET_HARD_REGNO_MODE_OK. In 32 bit mode, require that
DImode and DFmode be in even registers. For DImode, this makes some
of the insns easier to write, since you don't have to worry about a
DImode value in registers 3 & 4, producing a result in 4 & 5.
To make the code simpler, the hook now just references an
array built in override_options. */
static bool
microblaze_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return microblaze_hard_regno_mode_ok_p[mode][regno];
}
/* Return true if FUNC is an interrupt function as specified
by the "interrupt_handler" attribute. */
@ -3873,6 +3887,9 @@ microblaze_machine_dependent_reorg (void)
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG microblaze_machine_dependent_reorg
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK microblaze_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-microblaze.h"

14
gcc/config/microblaze/microblaze.h
View File

@ -295,20 +295,6 @@ extern enum pipeline_type microblaze_pipe;
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. In 32 bit mode, require that DImode and DFmode be in even
registers. For DImode, this makes some of the insns easier to
write, since you don't have to worry about a DImode value in
registers 3 & 4, producing a result in 4 & 5.
To make the code simpler HARD_REGNO_MODE_OK now just references an
array built in override_options. Because machmodes.h is not yet
included before this file is processed, the MODE bound can't be
expressed here. */
extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \

23
gcc/config/mips/mips.c
View File

@ -494,7 +494,7 @@ static int mips_base_align_jumps; /* align_jumps */
static int mips_base_align_functions; /* align_functions */
/* Index [M][R] is true if register R is allowed to hold a value of mode M. */
bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
static bool mips_hard_regno_mode_ok_p[MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
/* Index C is true if character C is a valid PRINT_OPERAND punctation
character. */
@ -12725,7 +12725,7 @@ mips_can_use_return_insn (void)
The result of this function is cached in mips_hard_regno_mode_ok. */
static bool
mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
mips_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode)
{
unsigned int size;
enum mode_class mclass;
@ -12830,6 +12830,14 @@ mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
return false;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
mips_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return mips_hard_regno_mode_ok_p[mode][regno];
}
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
bool
@ -12912,14 +12920,14 @@ mips_class_max_nregs (enum reg_class rclass, machine_mode mode)
COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
{
if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode))
size = MIN (size, 4);
AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
}
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
{
if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
if (mips_hard_regno_mode_ok (FP_REG_FIRST, mode))
{
if (MSA_SUPPORTED_MODE_P (mode))
size = MIN (size, UNITS_PER_MSA_REG);
@ -20110,8 +20118,8 @@ mips_option_override (void)
/* Set up mips_hard_regno_mode_ok. */
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
mips_hard_regno_mode_ok[mode][regno]
= mips_hard_regno_mode_ok_p (regno, (machine_mode) mode);
mips_hard_regno_mode_ok_p[mode][regno]
= mips_hard_regno_mode_ok_uncached (regno, (machine_mode) mode);
/* Function to allocate machine-dependent function status. */
init_machine_status = &mips_init_machine_status;
@ -22578,6 +22586,9 @@ mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK mips_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
mips_hard_regno_call_part_clobbered

4
gcc/config/mips/mips.h
View File

@ -1961,9 +1961,6 @@ FP_ASM_SPEC "\
#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
@ -3214,7 +3211,6 @@ struct mips_asm_switch {
};
extern const enum reg_class mips_regno_to_class[];
extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern const char *current_function_file; /* filename current function is in */
extern int num_source_filenames; /* current .file # */
extern struct mips_asm_switch mips_noreorder;

2
gcc/config/mmix/mmix.h
View File

@ -386,8 +386,6 @@ struct GTY(()) machine_function
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
/ UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
/* Note that no register can really be accessed in single-float mode, so
we *can* say 1 here. FIXME: Will TRT happen for single-float, or do
we have to punt to libgcc1.asm? */

1
gcc/config/mn10300/mn10300-protos.h
View File

@ -25,7 +25,6 @@ extern rtx mn10300_legitimize_reload_address (rtx, machine_mode,
int, int, int);
extern bool mn10300_function_value_regno_p (const unsigned int);
extern unsigned int mn10300_get_live_callee_saved_regs (unsigned int *);
extern bool mn10300_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool mn10300_modes_tieable (machine_mode, machine_mode);
extern const char *mn10300_output_add (rtx[3], bool);
extern void mn10300_print_operand (FILE *, rtx, int);

7
gcc/config/mn10300/mn10300.c
View File

@ -2626,7 +2626,9 @@ mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
return true;
}
bool
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
mn10300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (REGNO_REG_CLASS (regno) == FP_REGS
@ -3425,4 +3427,7 @@ mn10300_reorg (void)
#undef TARGET_FLAGS_REGNUM
#define TARGET_FLAGS_REGNUM CC_REG
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK mn10300_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;

9
gcc/config/mn10300/mn10300.h
View File

@ -233,15 +233,10 @@ extern enum processor_type mn10300_tune_cpu;
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
mn10300_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
mn10300_modes_tieable ((MODE1), (MODE2))

6
gcc/config/moxie/moxie.h
View File

@ -171,12 +171,6 @@ enum reg_class
/* We can't copy to or from our CC register. */
#define AVOID_CCMODE_COPIES 1
/* A C expression that is nonzero if it is permissible to store a
value of mode MODE in hard register number REGNO (or in several
registers starting with that one). All gstore registers are
equivalent, so we can set this to 1. */
#define HARD_REGNO_MODE_OK(R,M) 1
/* A C expression whose value is a register class containing hard
register REGNO. */
#define REGNO_REG_CLASS(R) ((R < MOXIE_PC) ? GENERAL_REGS : \

1
gcc/config/msp430/msp430-protos.h
View File

@ -29,7 +29,6 @@ void msp430_expand_helper (rtx *operands, const char *, bool);
void msp430_expand_prologue (void);
const char * msp430x_extendhisi (rtx *);
void msp430_fixup_compare_operands (machine_mode, rtx *);
int msp430_hard_regno_mode_ok (int, machine_mode);
int msp430_hard_regno_nregs (int, machine_mode);
int msp430_hard_regno_nregs_has_padding (int, machine_mode);
int msp430_hard_regno_nregs_with_padding (int, machine_mode);

12
gcc/config/msp430/msp430.c
View File

@ -933,12 +933,14 @@ msp430_hard_regno_nregs_with_padding (int regno ATTRIBUTE_UNUSED,
return msp430_hard_regno_nregs (regno, mode);
}
/* Implements HARD_REGNO_MODE_OK. */
int
msp430_hard_regno_mode_ok (int regno ATTRIBUTE_UNUSED,
machine_mode mode)
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK msp430_hard_regno_mode_ok
static bool
msp430_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return regno <= (ARG_POINTER_REGNUM - msp430_hard_regno_nregs (regno, mode));
return regno <= (ARG_POINTER_REGNUM
- (unsigned int) msp430_hard_regno_nregs (regno, mode));
}
/* Implements MODES_TIEABLE_P. */

3
gcc/config/msp430/msp430.h
View File

@ -335,9 +335,6 @@ typedef struct
#define HARD_REGNO_NREGS(REGNO, MODE) \
msp430_hard_regno_nregs (REGNO, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
msp430_hard_regno_mode_ok (REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) \
msp430_modes_tieable_p (MODE1, MODE2)

1
gcc/config/nds32/nds32-protos.h
View File

@ -31,7 +31,6 @@ extern void nds32_init_expanders (void);
/* -- How Values Fit in Registers. */
extern int nds32_hard_regno_nregs (int, machine_mode);
extern int nds32_hard_regno_mode_ok (int, machine_mode);
/* Register Classes. */

12
gcc/config/nds32/nds32.c
View File

@ -2753,17 +2753,21 @@ nds32_hard_regno_nregs (int regno ATTRIBUTE_UNUSED,
return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
}
int
nds32_hard_regno_mode_ok (int regno, machine_mode mode)
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Restrict double-word quantities to even register pairs. */
if (HARD_REGNO_NREGS (regno, mode) == 1
|| !((regno) & 1))
return 1;
return true;
return 0;
return false;
}
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
/* Register Classes. */

4
gcc/config/nds32/nds32.h
View File

@ -600,10 +600,6 @@ enum nds32_builtins
reg "regno" for holding a value of mode "mode". */
#define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
/* Value is 1 if hard register "regno" can hold a value
of machine-mode "mode". */
#define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
/* A C expression that is nonzero if a value of mode1
is accessible in mode2 without copying.
Define this macro to return nonzero in as many cases as possible

1
gcc/config/nios2/nios2.h
View File

@ -173,7 +173,6 @@
}
#define MODES_TIEABLE_P(MODE1, MODE2) 1
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

2
gcc/config/nvptx/nvptx.h
View File

@ -99,8 +99,6 @@
((void)(REG), (void)(MODE), 1)
#define CANNOT_CHANGE_MODE_CLASS(M1, M2, CLS) \
((void)(M1), (void)(M2), (void)(CLS), true)
#define HARD_REGNO_MODE_OK(REG, MODE) \
((void)(REG), (void)(MODE), true)
/* Register Classes. */
enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };

20
gcc/config/pa/pa.c
View File

@ -198,6 +198,7 @@ static unsigned int pa_section_type_flags (tree, const char *, int);
static bool pa_legitimate_address_p (machine_mode, rtx, bool);
static bool pa_callee_copies (cumulative_args_t, machine_mode,
const_tree, bool);
static bool pa_hard_regno_mode_ok (unsigned int, machine_mode);
/* The following extra sections are only used for SOM. */
static GTY(()) section *som_readonly_data_section;
@ -404,6 +405,9 @@ static size_t n_deferred_plabels = 0;
#undef TARGET_LRA_P
#define TARGET_LRA_P hook_bool_void_false
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK pa_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
/* Parse the -mfixed-range= option string. */
@ -9998,7 +10002,7 @@ pa_cannot_change_mode_class (machine_mode from, machine_mode to,
if (MAYBE_FP_REG_CLASS_P (rclass))
return true;
/* HARD_REGNO_MODE_OK places modes with sizes larger than a word
/* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word
in specific sets of registers. Thus, we cannot allow changing
to a larger mode when it's larger than a word. */
if (GET_MODE_SIZE (to) > UNITS_PER_WORD
@ -10010,13 +10014,13 @@ pa_cannot_change_mode_class (machine_mode from, machine_mode to,
/* Returns TRUE if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be FALSE for correct output.
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be FALSE for correct output.
We should return FALSE for QImode and HImode because these modes
are not ok in the floating-point registers. However, this prevents
tieing these modes to SImode and DImode in the general registers.
So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
So, this isn't a good idea. We rely on TARGET_HARD_REGNO_MODE_OK and
CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
in the floating-point registers. */
@ -10756,4 +10760,12 @@ pa_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
return !TARGET_CALLER_COPIES;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
pa_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return PA_HARD_REGNO_MODE_OK (regno, mode);
}
#include "gt-pa.h"

8
gcc/config/pa/pa.h
View File

@ -324,10 +324,10 @@ typedef struct GTY(()) machine_function
when given unaligned data. */
#define STRICT_ALIGNMENT 1
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
/* Value is 1 if it is a good idea to tie two pseudo registers when one
has mode MODE1 and one has mode MODE2.
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
pa_modes_tieable_p (MODE1, MODE2)

2
gcc/config/pa/pa32-regs.h
View File

@ -206,7 +206,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
supported under HP-UX using libcalls. Since TFmode values are passed
by reference, they never need to be loaded into the floating-point
registers. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
: (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE) \
: !TARGET_PA_11 && FP_REGNO_P (REGNO) \

2
gcc/config/pa/pa64-regs.h
View File

@ -149,7 +149,7 @@ along with GCC; see the file COPYING3. If not see
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the HP-PA, the cpu registers can hold any mode. We
force this to be an even register if it cannot hold the full mode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
: (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE) \

22
gcc/config/pdp11/pdp11.c
View File

@ -235,6 +235,9 @@ static bool pdp11_scalar_mode_supported_p (scalar_mode);
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK pdp11_hard_regno_mode_ok
/* A helper function to determine if REGNO should be saved in the
current function's stack frame. */
@ -1925,4 +1928,23 @@ pdp11_branch_cost ()
return (TARGET_BRANCH_CHEAP ? 0 : 1);
}
/* Implement TARGET_HARD_REGNO_MODE_OK. On the pdp, the cpu registers
can hold any mode other than float (because otherwise we may end up
being asked to move from CPU to FPU register, which isn't a valid
operation on the PDP11). For CPU registers, check alignment.
FPU accepts SF and DF but actually holds a DF - simplifies life! */
static bool
pdp11_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (regno <= PC_REGNUM)
return (GET_MODE_BITSIZE (mode) <= 16
|| (GET_MODE_BITSIZE (mode) >= 32
&& !(regno & 1)
&& !FLOAT_MODE_P (mode)));
return FLOAT_MODE_P (mode);
}
struct gcc_target targetm = TARGET_INITIALIZER;

20
gcc/config/pdp11/pdp11.h
View File

@ -176,26 +176,10 @@ extern const struct real_format pdp11_d_format;
:1)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the pdp, the cpu registers can hold any mode other than float
(because otherwise we may end up being asked to move from CPU to FPU
register, which isn't a valid operation on the PDP11).
For CPU registers, check alignment.
FPU accepts SF and DF but actually holds a DF - simplifies life!
*/
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(((REGNO) <= PC_REGNUM)? \
((GET_MODE_BITSIZE(MODE) <= 16) \
|| (GET_MODE_BITSIZE(MODE) >= 32 && \
!((REGNO) & 1) && !FLOAT_MODE_P (MODE))) \
:FLOAT_MODE_P (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) 0
/* Specify the registers used for certain standard purposes.

1
gcc/config/powerpcspe/powerpcspe-protos.h
View File

@ -254,7 +254,6 @@ const char * rs6000_xcoff_strip_dollar (const char *);
void rs6000_final_prescan_insn (rtx_insn *, rtx *operand, int num_operands);
extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
extern unsigned char rs6000_class_max_nregs[][LIM_REG_CLASSES];
extern unsigned char rs6000_hard_regno_nregs[][FIRST_PSEUDO_REGISTER];

20
gcc/config/powerpcspe/powerpcspe.c
View File

@ -210,7 +210,8 @@ static bool rs6000_returns_struct;
#endif
/* Value is TRUE if register/mode pair is acceptable. */
bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
static bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Maximum number of registers needed for a given register class and mode. */
unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
@ -1972,6 +1973,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
rs6000_hard_regno_call_part_clobbered
@ -2060,7 +2064,7 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
static int
rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
@ -2160,6 +2164,14 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return rs6000_hard_regno_mode_ok_p[mode][regno];
}
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
static bool
@ -3684,10 +3696,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_hard_regno_nregs[m][r]
= rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
/* Precalculate HARD_REGNO_MODE_OK. */
/* Precalculate TARGET_HARD_REGNO_MODE_OK. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_hard_regno_mode_ok (r, (machine_mode)m))
if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
rs6000_hard_regno_mode_ok_p[m][r] = true;
/* Precalculate CLASS_MAX_NREGS sizes. */

9
gcc/config/powerpcspe/powerpcspe.h
View File

@ -1330,15 +1330,10 @@ enum data_align { align_abi, align_opt, align_both };
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
/* Value is TRUE if hard register REGNO can hold a value of
machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output.
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output.
PTImode cannot tie with other modes because PTImode is restricted to even
GPR registers, and TImode can go in any GPR as well as VSX registers (PR

1
gcc/config/riscv/riscv-protos.h
View File

@ -39,7 +39,6 @@ enum riscv_symbol_type {
extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
extern bool riscv_hard_regno_mode_ok_p (unsigned int, machine_mode);
extern int riscv_address_insns (rtx, machine_mode, bool);
extern int riscv_const_insns (rtx);
extern int riscv_split_const_insns (rtx);

9
gcc/config/riscv/riscv.c
View File

@ -3519,10 +3519,10 @@ riscv_register_move_cost (machine_mode mode,
return SECONDARY_MEMORY_NEEDED (from, to, mode) ? 8 : 2;
}
/* Return true if register REGNO can store a value of mode MODE. */
/* Implement TARGET_HARD_REGNO_MODE_OK. */
bool
riscv_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
static bool
riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
unsigned int nregs = riscv_hard_regno_nregs (regno, mode);
@ -4083,6 +4083,9 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN riscv_expand_builtin
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"

4
gcc/config/riscv/riscv.h
View File

@ -296,9 +296,6 @@ along with GCC; see the file COPYING3. If not see
#define HARD_REGNO_NREGS(REGNO, MODE) riscv_hard_regno_nregs (REGNO, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
riscv_hard_regno_mode_ok_p (REGNO, MODE)
/* Don't allow floating-point modes to be tied, since type punning of
single-precision and double-precision is implementation defined. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
@ -864,7 +861,6 @@ while (0)
#ifndef USED_FOR_TARGET
extern const enum reg_class riscv_regno_to_class[];
extern bool riscv_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern bool riscv_slow_unaligned_access;
#endif

1
gcc/config/rl78/rl78-protos.h
View File

@ -29,7 +29,6 @@ void rl78_expand_eh_epilogue (rtx);
void rl78_expand_epilogue (void);
void rl78_expand_prologue (void);
int rl78_far_p (rtx x);
int rl78_hard_regno_mode_ok (int, machine_mode);
int rl78_hard_regno_nregs (int, machine_mode);
bool rl78_hl_b_c_addr_p (rtx);
int rl78_initial_elimination_offset (int, int);

22
gcc/config/rl78/rl78.c
View File

@ -459,34 +459,36 @@ rl78_hard_regno_nregs (int regno, machine_mode mode)
return ((GET_MODE_SIZE (mode) + rs - 1) / rs);
}
/* Implements HARD_REGNO_MODE_OK. */
int
rl78_hard_regno_mode_ok (int regno, machine_mode mode)
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK rl78_hard_regno_mode_ok
static bool
rl78_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
int s = GET_MODE_SIZE (mode);
if (s < 1)
return 0;
return false;
/* These are not to be used by gcc. */
if (regno == 23 || regno == ES_REG || regno == CS_REG)
return 0;
return false;
/* $fp can always be accessed as a 16-bit value. */
if (regno == FP_REG && s == 2)
return 1;
return true;
if (regno < SP_REG)
{
/* Since a reg-reg move is really a reg-mem move, we must
enforce alignment. */
if (s > 1 && (regno % 2))
return 0;
return 1;
return false;
return true;
}
if (s == CC_REGNUM)
return (mode == BImode);
/* All other registers must be accessed in their natural sizes. */
if (s == register_sizes [regno])
return 1;
return 0;
return true;
return false;
}
/* Simplify_gen_subreg() doesn't handle memory references the way we

3
gcc/config/rl78/rl78.h
View File

@ -410,9 +410,6 @@ typedef unsigned int CUMULATIVE_ARGS;
#define HARD_REGNO_NREGS(REGNO, MODE) \
rl78_hard_regno_nregs (REGNO, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
rl78_hard_regno_mode_ok (REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) \
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \

1
gcc/config/rs6000/rs6000-protos.h
View File

@ -255,7 +255,6 @@ const char * rs6000_xcoff_strip_dollar (const char *);
void rs6000_final_prescan_insn (rtx_insn *, rtx *operand, int num_operands);
extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
extern unsigned char rs6000_class_max_nregs[][LIM_REG_CLASSES];
extern unsigned char rs6000_hard_regno_nregs[][FIRST_PSEUDO_REGISTER];

20
gcc/config/rs6000/rs6000.c
View File

@ -201,7 +201,8 @@ static bool rs6000_returns_struct;
#endif
/* Value is TRUE if register/mode pair is acceptable. */
bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
static bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Maximum number of registers needed for a given register class and mode. */
unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
@ -1962,6 +1963,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_OPTION_FUNCTION_VERSIONS
#define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
rs6000_hard_regno_call_part_clobbered
@ -2034,7 +2038,7 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
static int
rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
@ -2127,6 +2131,14 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return rs6000_hard_regno_mode_ok_p[mode][regno];
}
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
static bool
@ -3598,10 +3610,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_hard_regno_nregs[m][r]
= rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
/* Precalculate HARD_REGNO_MODE_OK. */
/* Precalculate TARGET_HARD_REGNO_MODE_OK. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
if (rs6000_hard_regno_mode_ok (r, (machine_mode)m))
if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
rs6000_hard_regno_mode_ok_p[m][r] = true;
/* Precalculate CLASS_MAX_NREGS sizes. */

9
gcc/config/rs6000/rs6000.h
View File

@ -1258,15 +1258,10 @@ enum data_align { align_abi, align_opt, align_both };
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
/* Value is TRUE if hard register REGNO can hold a value of
machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output.
If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
and MODE2, for any hard reg, then this must be 0 for correct output.
PTImode cannot tie with other modes because PTImode is restricted to even
GPR registers, and TImode can go in any GPR as well as VSX registers (PR

10
gcc/config/rx/rx.c
View File

@ -3434,6 +3434,13 @@ rx_atomic_sequence::~rx_atomic_sequence (void)
emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg));
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
rx_hard_regno_mode_ok (unsigned int regno, machine_mode)
{
return REGNO_REG_CLASS (regno) == GR_REGS;
}
#undef TARGET_NARROW_VOLATILE_BITFIELD
#define TARGET_NARROW_VOLATILE_BITFIELD rx_narrow_volatile_bitfield
@ -3588,6 +3595,9 @@ rx_atomic_sequence::~rx_atomic_sequence (void)
#undef TARGET_LRA_P
#define TARGET_LRA_P rx_enable_lra
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK rx_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rx.h"

3
gcc/config/rx/rx.h
View File

@ -333,9 +333,6 @@ typedef unsigned int CUMULATIVE_ARGS;
#define HARD_REGNO_NREGS(REGNO, MODE) CLASS_MAX_NREGS (0, MODE)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(REGNO_REG_CLASS (REGNO) == GR_REGS)
#define MODES_TIEABLE_P(MODE1, MODE2) \
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \

1
gcc/config/s390/s390-protos.h
View File

@ -47,7 +47,6 @@ extern bool s390_can_use_simple_return_insn (void);
extern bool s390_can_use_return_insn (void);
extern void s390_function_profiler (FILE *, int);
extern void s390_set_has_landing_pad_p (bool);
extern bool s390_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
extern int s390_class_max_nregs (enum reg_class, machine_mode);
extern int s390_cannot_change_mode_class (machine_mode, machine_mode,

9
gcc/config/s390/s390.c
View File

@ -87,6 +87,8 @@ along with GCC; see the file COPYING3. If not see
/* This file should be included last. */
#include "target-def.h"
static bool s390_hard_regno_mode_ok (unsigned int, machine_mode);
/* Remember the last target of s390_set_current_function. */
static GTY(()) tree s390_previous_fndecl;
@ -10386,9 +10388,9 @@ s390_optimize_nonescaping_tx (void)
return;
}
/* Return true if it is legal to put a value with MODE into REGNO. */
/* Implement TARGET_HARD_REGNO_MODE_OK. */
bool
static bool
s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (!TARGET_VX && VECTOR_NOFP_REGNO_P (regno))
@ -15961,6 +15963,9 @@ s390_asan_shadow_offset (void)
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK s390_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
s390_hard_regno_call_part_clobbered

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