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[ARM] Add initial support for Cortex-A73

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* config/arm/arm.c (arm_cortex_a73_tune): New struct.
        * config/arm/arm-cores.def (cortex-a73): New entry.
        (cortex-a73.cortex-a35): Likewise.
        (cortex-a73.cortex-a53): Likewise.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/arm-tune.md: Likewise.
        * config/arm/bpabi.h (BE8_LINK_SPEC): Handle mcpu=cortex-a73,
        mcpu=cortex-a73.cortex-a35 and mcpu=cortex-a73.cortex-a53.
        * config/arm/t-aprofile: Handle mcpu=cortex-a73,
        mcpu=cortex-a73.cortex-a35 and mcpu=cortex-a73.cortex-a53.
        * doc/invoke.texi (ARM Options): Document cortex-a73,
        cortex-a73.cortex-a35 and cortex-a73.cortex-a53.

From-SVN: r237681
This commit is contained in:
Kyrylo Tkachov 2016-06-22 09:25:54 +00:00 committed by Kyrylo Tkachov
parent 7320a4b519
commit f9405b6348
8 changed files with 66 additions and 4 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2016-06-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_cortex_a73_tune): New struct.
* config/arm/arm-cores.def (cortex-a73): New entry.
(cortex-a73.cortex-a35): Likewise.
(cortex-a73.cortex-a53): Likewise.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/bpabi.h (BE8_LINK_SPEC): Handle mcpu=cortex-a73,
mcpu=cortex-a73.cortex-a35 and mcpu=cortex-a73.cortex-a53.
* config/arm/t-aprofile: Handle mcpu=cortex-a73,
mcpu=cortex-a73.cortex-a35 and mcpu=cortex-a73.cortex-a53.
* doc/invoke.texi (ARM Options): Document cortex-a73,
cortex-a73.cortex-a35 and cortex-a73.cortex-a53.
2016-06-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (cortexa73_tunings): New struct.

4
gcc/config/arm/arm-cores.def
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@ -171,6 +171,7 @@ ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
@ -178,3 +179,6 @@ ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCH
/* V8 big.LITTLE implementations */
ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)

9
gcc/config/arm/arm-tables.opt
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@ -321,6 +321,9 @@ Enum(processor_type) String(cortex-a57) Value(cortexa57)
EnumValue
Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
Enum(processor_type) String(cortex-a73) Value(cortexa73)
EnumValue
Enum(processor_type) String(exynos-m1) Value(exynosm1)
@ -336,6 +339,12 @@ Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53)
EnumValue
Enum(processor_type) String(cortex-a72.cortex-a53) Value(cortexa72cortexa53)
EnumValue
Enum(processor_type) String(cortex-a73.cortex-a35) Value(cortexa73cortexa35)
EnumValue
Enum(processor_type) String(cortex-a73.cortex-a53) Value(cortexa73cortexa53)
Enum
Name(arm_arch) Type(int)
Known ARM architectures (for use with the -march= option):

5
gcc/config/arm/arm-tune.md
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@ -34,6 +34,7 @@
cortexm3,marvell_pj4,cortexa15cortexa7,
cortexa17cortexa7,cortexa32,cortexa35,
cortexa53,cortexa57,cortexa72,
exynosm1,qdf24xx,xgene1,
cortexa57cortexa53,cortexa72cortexa53"
cortexa73,exynosm1,qdf24xx,
xgene1,cortexa57cortexa53,cortexa72cortexa53,
cortexa73cortexa35,cortexa73cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))

23
gcc/config/arm/arm.c
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@ -2125,6 +2125,29 @@ const struct tune_params arm_cortex_a12_tune =
tune_params::SCHED_AUTOPREF_OFF
};
const struct tune_params arm_cortex_a73_tune =
{
arm_9e_rtx_costs,
&cortexa57_extra_costs,
NULL, /* Sched adj cost. */
arm_default_branch_cost,
&arm_default_vec_cost, /* Vectorizer costs. */
1, /* Constant limit. */
2, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
tune_params::DISPARAGE_FLAGS_ALL,
tune_params::PREF_NEON_64_FALSE,
tune_params::PREF_NEON_STRINGOPS_TRUE,
FUSE_OPS (tune_params::FUSE_AES_AESMC | tune_params::FUSE_MOVW_MOVT),
tune_params::SCHED_AUTOPREF_FULL
};
/* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single
cycle to execute each. An LDR from the constant pool also takes two cycles
to execute, but mildly increases pipelining opportunity (consecutive

6
gcc/config/arm/bpabi.h
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@ -75,6 +75,9 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
|mcpu=cortex-a73 \
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
|mcpu=qdf24xx \
|mcpu=xgene1 \
@ -105,6 +108,9 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
|mcpu=cortex-a73 \
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
|mcpu=qdf24xx \
|mcpu=xgene1 \

3
gcc/config/arm/t-aprofile
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@ -93,6 +93,9 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1

5
gcc/doc/invoke.texi
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@ -14158,7 +14158,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
@samp{cortex-a72}, @samp{cortex-r4},
@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
@samp{cortex-m7},
@samp{cortex-m4},
@ -14180,7 +14180,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}.
@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
performance for a blend of processors within architecture @var{arch}.