Fix adddi3.
From-SVN: r8352
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@ -2343,19 +2343,25 @@
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;;- add instructions
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,o,o,o")
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(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,or,riF,riF,o")
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(match_operand:DI 2 "general_operand" "o,riF,o,oriF,riF,o,o")))
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(clobber (match_scratch:SI 3 "=X,X,&r,X,X,&r,&r"))]
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[(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,ro,o,&r,o,o,o")
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(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,o,riF,o,or,riF,riF,o")
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(match_operand:DI 2 "general_operand" "o,riF,o,0,0,0,oriF,riF,o,o")))
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(clobber (match_scratch:SI 3 "=X,X,&r,X,X,&r,X,X,&r,&r"))]
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""
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"*
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{
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rtx low[3], high[3], xops[7];
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rtx low[3], high[3], xops[7], temp;
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CC_STATUS_INIT;
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split_di (operands, 3, low, high);
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if (rtx_equal_p (operands[0], operands[2]))
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{
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temp = operands[1];
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operands[1] = operands[2];
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operands[2] = temp;
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}
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split_di (operands, 3, low, high);
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if (!rtx_equal_p (operands[0], operands[1]))
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{
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xops[0] = high[0];
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@ -2383,7 +2389,7 @@
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}
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}
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if (GET_CODE (operands[3]) == REG)
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if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
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{
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xops[0] = high[0];
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xops[1] = low[0];
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