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sparc.c (sparc_override_options): If not TARGET_FPU, turn off TARGET_VIS. 

* config/sparc/sparc.c (sparc_override_options): If not
	TARGET_FPU, turn off TARGET_VIS.
	* config/sparc/sparc.h (TARGET_SWITCHES): Add no-vis.
	(LEGITIMATE_CONSTANT_P): Allow SF/DF mode zero when TARGET_VIS.
	* config/sparc/sparc.md (movsi_insn): Use fzeros not fzero.
	(movdi_insn_sp64): Add VIS fzero alternative.
	(clear_sf, clear_df): New VIS patterns.
	(movsf, movdf expanders): Allow fp_zero_operand flat out when
	TARGET_VIS.
	(one_cmpldi2_sp64): Provide new fnot1 VIS alternative.

From-SVN: r21996
This commit is contained in:
Jakub Jelinek 1998-08-26 08:19:46 +02:00 committed by David S. Miller
parent 04069e5c0c
commit f952a23816
4 changed files with 86 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
Wed Aug 26 05:09:27 1998 Jakub Jelinek <jj@sunsite.ms.mff.cuni.cz>
* config/sparc/sparc.c (sparc_override_options): If not
TARGET_FPU, turn off TARGET_VIS.
* config/sparc/sparc.h (TARGET_SWITCHES): Add no-vis.
(LEGITIMATE_CONSTANT_P): Allow SF/DF mode zero when TARGET_VIS.
* config/sparc/sparc.md (movsi_insn): Use fzeros not fzero.
(movdi_insn_sp64): Add VIS fzero alternative.
(clear_sf, clear_df): New VIS patterns.
(movsf, movdf expanders): Allow fp_zero_operand flat out when
TARGET_VIS.
(one_cmpldi2_sp64): Provide new fnot1 VIS alternative.
Tue Aug 25 10:57:41 1998 Mark Mitchell <mark@markmitchell.com>
* loop.c (n_times_set, n_times_used, may_not_optimize,

4
gcc/config/sparc/sparc.c
View File

@ -287,6 +287,10 @@ sparc_override_options ()
/* Don't use stack biasing in 32 bit mode. */
if (TARGET_ARCH32)
target_flags &= ~MASK_STACK_BIAS;
/* Don't allow -mvis if FPU is disabled. */
if (! TARGET_FPU)
target_flags &= ~MASK_VIS;
/* Validate -malign-loops= value, or provide default. */
if (sparc_align_loops_string)

10
gcc/config/sparc/sparc.h
View File

@ -501,6 +501,7 @@ extern int target_flags;
{"v8plus", MASK_V8PLUS}, \
{"no-v8plus", -MASK_V8PLUS}, \
{"vis", MASK_VIS}, \
{"no-vis", -MASK_VIS}, \
/* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
{"cypress", 0}, \
{"sparclite", 0}, \
@ -2266,10 +2267,13 @@ extern struct rtx_def *sparc_builtin_saveregs ();
#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
/* Nonzero if the constant value X is a legitimate general operand.
Anything can be made to work except floating point constants. */
Anything can be made to work except floating point constants.
If TARGET_VIS, 0.0 can be made to work as well. */
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
(TARGET_VIS && (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode) && \
fp_zero_operand (X)))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.

73
gcc/config/sparc/sparc.md
View File

@ -2152,7 +2152,7 @@
ld\\t%1, %0
st\\t%r1, %0
st\\t%1, %0
fzero\\t%0"
fzeros\\t%0"
[(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove")
(set_attr "length" "1")])
@ -2369,8 +2369,8 @@
(set_attr "length" "1")])
(define_insn "*movdi_insn_sp64"
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m")
(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))]
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m,b")
(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e,J"))]
"TARGET_ARCH64 &&
(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
@ -2382,8 +2382,9 @@
stx\\t%r1, %0
fmovd\\t%1, %0
ldd\\t%1, %0
std\\t%1, %0"
[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
std\\t%1, %0
fzero\\t%0"
[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove")
(set_attr "length" "1")])
;; ??? revisit this...
@ -2731,6 +2732,17 @@
;; Floating point move insns
(define_insn "*clear_sf"
[(set (match_operand:SF 0 "general_operand" "=f")
(match_operand:SF 1 "" ""))]
"TARGET_VIS
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& GET_CODE (operands[0]) == REG
&& fp_zero_operand (operands[1])"
"fzeros\\t%0"
[(set_attr "type" "fpmove")
(set_attr "length" "1")])
(define_insn "*movsf_const_intreg"
[(set (match_operand:SF 0 "general_operand" "=f,r")
(match_operand:SF 1 "" "m,F"))]
@ -2809,6 +2821,11 @@
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
if (TARGET_VIS
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& fp_zero_operand (operands[1]))
goto movsf_is_ok;
/* emit_group_store will send such bogosity to us when it is
not storing directly into memory. So fix this up to avoid
crashes in output_constant_pool. */
@ -2885,10 +2902,37 @@
[(set_attr "type" "move,load,store")
(set_attr "length" "1")])
(define_insn "*movdf_const_intreg"
(define_insn "*clear_df"
[(set (match_operand:DF 0 "general_operand" "=e")
(match_operand:DF 1 "" ""))]
"TARGET_VIS
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& GET_CODE (operands[0]) == REG
&& fp_zero_operand (operands[1])"
"fzero\\t%0"
[(set_attr "type" "fpmove")
(set_attr "length" "1")])
(define_insn "*movdf_const_intreg_sp32"
[(set (match_operand:DF 0 "general_operand" "=e,e,r")
(match_operand:DF 1 "" "T,o,F"))]
"TARGET_FPU
"TARGET_FPU && ! TARGET_ARCH64
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& GET_CODE (operands[0]) == REG"
"*
{
if (which_alternative == 0)
return \"ldd\\t%1, %0\";
else
return \"#\";
}"
[(set_attr "type" "move")
(set_attr "length" "1")])
(define_insn "*movdf_const_intreg_sp64"
[(set (match_operand:DF 0 "general_operand" "=e,e,r")
(match_operand:DF 1 "" "m,o,F"))]
"TARGET_FPU && TARGET_ARCH64
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& GET_CODE (operands[0]) == REG"
"*
@ -2951,6 +2995,11 @@
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
if (TARGET_VIS
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& fp_zero_operand (operands[1]))
goto movdf_is_ok;
/* emit_group_store will send such bogosity to us when it is
not storing directly into memory. So fix this up to avoid
crashes in output_constant_pool. */
@ -6321,11 +6370,13 @@
operands[5] = gen_lowpart (SImode, operands[1]);")
(define_insn "*one_cmpldi2_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")))]
[(set (match_operand:DI 0 "register_operand" "=r,b")
(not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
"TARGET_ARCH64"
"xnor\\t%%g0, %1, %0"
[(set_attr "type" "unary")
"@
xnor\\t%%g0, %1, %0
fnot1\\t%1, %0"
[(set_attr "type" "unary,fp")
(set_attr "length" "1")])
(define_expand "one_cmplsi2"