c4x.md: Define mode for remaining unspec operators.
* config/c4x/c4x.md: Define mode for remaining unspec operators. * config/c4x/c4x.c (dst_operand): Use nonimmediate_operand. From-SVN: r30000
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Fri Oct 15 18:36:07 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.md: Define mode for remaining unspec operators.
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* config/c4x/c4x.c (dst_operand): Use nonimmediate_operand.
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Thu Oct 14 22:14:23 1999 Richard Henderson <rth@cygnus.com>
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* i386.md (movstricthi_1): Allow r/r.
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@ -593,6 +593,7 @@ c4x_function_arg (cum, mode, type, named)
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return NULL_RTX;
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}
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void
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c4x_va_start (stdarg_p, valist, nextarg)
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int stdarg_p;
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@ -604,9 +605,9 @@ c4x_va_start (stdarg_p, valist, nextarg)
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std_expand_builtin_va_start (stdarg_p, valist, nextarg);
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}
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/* C[34]x arguments grow in weird ways (downwards) that the standard
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varargs stuff can't handle. */
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rtx
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c4x_va_arg (valist, type)
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tree valist, type;
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@ -620,6 +621,7 @@ c4x_va_arg (valist, type)
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return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
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}
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static int
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c4x_isr_reg_used_p (regno)
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int regno;
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@ -3059,7 +3061,6 @@ symbolic_address_operand (op, mode)
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}
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}
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/* Check dst operand of a move instruction. */
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int
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dst_operand (op, mode)
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@ -3073,7 +3074,7 @@ dst_operand (op, mode)
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if (REG_P (op))
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return reg_operand (op, mode);
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return memory_operand (op, mode);
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return nonimmediate_operand (op, mode);
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}
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@ -2639,7 +2639,7 @@
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(define_insn "*lshlqi3_clobber"
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[(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
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(ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
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(unspec [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] 3)))
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(unspec:QI [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] 3)))
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(clobber (reg:CC 21))]
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"valid_operands (ASHIFT, operands, QImode)"
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"@
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@ -3587,7 +3587,7 @@
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; Inlined float square root for C4x
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(define_expand "sqrtqf2_inline"
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[(parallel [(set (match_dup 2)
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(unspec [(match_operand:QF 1 "src_operand" "")] 10))
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(unspec:QF [(match_operand:QF 1 "src_operand" "")] 10))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1)))
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(clobber (reg:CC_NOOV 21))])
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@ -3610,7 +3610,7 @@
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(parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1)))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_operand:QF 0 "reg_operand" "")
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(unspec [(match_dup 4)] 6))
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(unspec:QF [(match_dup 4)] 6))
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(clobber (reg:CC_NOOV 21))])]
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"! TARGET_C3X"
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"if (! reload_in_progress
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@ -3836,7 +3836,7 @@
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; Inlined float divide for C4x
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(define_expand "divqf3_inline"
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[(parallel [(set (match_dup 3)
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(unspec [(match_operand:QF 2 "src_operand" "")] 5))
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(unspec:QF [(match_operand:QF 2 "src_operand" "")] 5))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
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(clobber (reg:CC_NOOV 21))])
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@ -3855,7 +3855,7 @@
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(match_dup 3)))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_operand:QF 0 "reg_operand" "")
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(unspec [(match_dup 3)] 6))
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(unspec:QF [(match_dup 3)] 6))
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(clobber (reg:CC_NOOV 21))])]
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"! TARGET_C3X"
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"if (! reload_in_progress
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@ -5267,7 +5267,7 @@
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(match_operand:HF 1 "reg_operand" ""))]
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"reload_completed"
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[(set (match_dup 2) (float_truncate:QF (match_dup 1)))
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(set (match_dup 3) (unspec [(match_dup 1)] 9))]
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(set (match_dup 3) (unspec:QI [(match_dup 1)] 9))]
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"operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode);
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operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode);
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PUT_MODE (operands[2], QFmode);
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@ -5337,7 +5337,7 @@
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[(set (mem:QF (pre_inc:QI (reg:QI 20)))
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(float_truncate:QF (match_dup 0)))
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(set (mem:QI (pre_inc:QI (reg:QI 20)))
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(unspec [(match_dup 0)] 9))]
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(unspec:QI [(match_dup 0)] 9))]
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"")
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(define_insn "pushhf_trunc"
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@ -5519,7 +5519,7 @@
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; Inlined float square root for C4x
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(define_expand "sqrthf2_inline"
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[(parallel [(set (match_dup 2)
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(unspec [(match_operand:HF 1 "reg_operand" "")] 10))
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(unspec:HF [(match_operand:HF 1 "reg_operand" "")] 10))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1)))
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(clobber (reg:CC_NOOV 21))])
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; Inlined float divide for C4x
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(define_expand "divhf3_inline"
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[(parallel [(set (match_dup 3)
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(unspec [(match_operand:HF 2 "reg_operand" "")] 5))
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(unspec:HF [(match_operand:HF 2 "reg_operand" "")] 5))
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(clobber (reg:CC_NOOV 21))])
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(parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
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(clobber (reg:CC_NOOV 21))])
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@ -6261,7 +6261,7 @@
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/* If the shift count is greater than 32 this will do an arithmetic
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right shift. However, we need a logical right shift. */
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(parallel [(set (match_dup 9)
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(ashift:QI (match_dup 4) (unspec [(match_dup 10)] 3)))
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(ashift:QI (match_dup 4) (unspec:QI [(match_dup 10)] 3)))
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(clobber (reg:CC 21))])
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(set (match_dup 6) (match_dup 8))
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(parallel [(set (match_dup 5)
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(match_operand:HI 1 "src_operand" "")))]
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"! reload_completed"
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[(parallel [(set (reg:CC 21)
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(unspec [(compare:CC (match_dup 0)
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(match_dup 1))] 4))
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(unspec:CC [(compare:CC (match_dup 0)
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(match_dup 1))] 4))
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(clobber (match_scratch:QI 2 ""))
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(clobber (match_scratch:QI 3 ""))])]
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"")
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(match_operand:HI 1 "src_operand" "")))]
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"! reload_completed"
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[(parallel [(set (reg:CC_NOOV 21)
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(unspec [(compare:CC_NOOV (match_dup 0)
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(match_dup 1))] 4))
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(unspec:CC_NOOV [(compare:CC_NOOV (match_dup 0)
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(match_dup 1))] 4))
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(clobber (match_scratch:QI 2 ""))
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(clobber (match_scratch:QI 3 ""))])]
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"")
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