diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 090dbcff61d..1367a2cb779 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4225,23 +4225,14 @@
   operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1);
 })
 
-(define_insn "*rotl<mode>3_insert_4"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
-			  (match_operand:GPR 4 "const_int_operand" "n"))
-		 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			       (match_operand:SI 2 "const_int_operand" "n"))))]
-  "<MODE>mode == SImode &&
-   GET_MODE_PRECISION (<MODE>mode)
-   == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))"
-{
-  operands[2] = GEN_INT (GET_MODE_PRECISION (<MODE>mode)
-			 - INTVAL (operands[2]));
-  if (<MODE>mode == SImode)
-    return "rlwimi %0,%1,%h2,32-%h2,31";
-  else
-    return "rldimi %0,%1,%H2,64-%H2";
-}
+(define_insn "*rotlsi3_insert_4"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+			(match_operand:SI 4 "const_int_operand" "n"))
+		(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
+  "INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4])) == 32"
+  "rlwimi %0,%1,32-%h2,%h2,31"
   [(set_attr "type" "insert")])
 
 (define_insn "*rotlsi3_insert_5"