From f9764ea128c99ba1c10de21a092266cd7da8700a Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Mon, 27 Jun 2022 21:50:26 -0500 Subject: [PATCH] rs6000: Simplify *rotl3_insert_4 by removing DImode define_insn *rotl3_insert_4 use mode iterator GPR which consists of SImode and conditional DImode, but the condition of this define_insn requires the mode should be SImode. By further checking, it's found that the rldimi instruction can not be used for this pattern since the required mask can not be represented correctly. We can have the fixed mask end 31 with rlwimi, but can not have the fixed mask end 63 with rldimi as it has to be (63 - SH) always. So this patch simplifies this define_insn to use SImode only. gcc/ChangeLog: * config/rs6000/rs6000.md (*rotl3_insert_4): Replace mode iterator GPR with SImode, adjust the condition and output template, rename to ... (*rotlsi3_insert_4): ... this. --- gcc/config/rs6000/rs6000.md | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 090dbcff61d..1367a2cb779 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4225,23 +4225,14 @@ operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1); }) -(define_insn "*rotl3_insert_4" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0") - (match_operand:GPR 4 "const_int_operand" "n")) - (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "const_int_operand" "n"))))] - "mode == SImode && - GET_MODE_PRECISION (mode) - == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))" -{ - operands[2] = GEN_INT (GET_MODE_PRECISION (mode) - - INTVAL (operands[2])); - if (mode == SImode) - return "rlwimi %0,%1,%h2,32-%h2,31"; - else - return "rldimi %0,%1,%H2,64-%H2"; -} +(define_insn "*rotlsi3_insert_4" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0") + (match_operand:SI 4 "const_int_operand" "n")) + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "n"))))] + "INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4])) == 32" + "rlwimi %0,%1,32-%h2,%h2,31" [(set_attr "type" "insert")]) (define_insn "*rotlsi3_insert_5"