h8300.c (output_logical_op): Simplify and optimize the handling of SImode.
* config/h8300/h8300.c (output_logical_op): Simplify and optimize the handling of SImode. * config/h8300/h8300.c (compute_logical_op_length): Update accordingly. * config/h8300/h8300.c (compute_logical_op_cc): Likewise. From-SVN: r60995
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
c93721124b
commit
f9ac2f95ec
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@ -1,3 +1,11 @@
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2003-01-07 Kazu Hirata <kazu@cs.umass.edu>
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* config/h8300/h8300.c (output_logical_op): Simplify and
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optimize the handling of SImode.
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* config/h8300/h8300.c (compute_logical_op_length): Update
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accordingly.
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* config/h8300/h8300.c (compute_logical_op_cc): Likewise.
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2003-01-07 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (mips_va_arg): In the EABI code, apply the
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@ -2061,6 +2061,13 @@ output_logical_op (mode, operands)
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/* The determinant of the algorithm. If we perform an AND, 0
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affects a bit. Otherwise, 1 affects a bit. */
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const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
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/* Break up DET into pieces. */
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const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
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const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
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const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
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const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
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int lower_half_easy_p = 0;
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int upper_half_easy_p = 0;
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/* The name of an insn. */
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const char *opname;
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char insn_buf[100];
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@ -2108,20 +2115,25 @@ output_logical_op (mode, operands)
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}
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break;
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case SImode:
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/* First, see if we can finish with one insn.
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if (TARGET_H8300H || TARGET_H8300S)
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{
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/* Determine if the lower half can be taken care of in no more
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than two bytes. */
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lower_half_easy_p = (b0 == 0
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|| b1 == 0
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|| (code != IOR && w0 == 0xffff));
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If code is either AND or XOR, we exclude two special cases,
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0xffffff00 and 0xffff00ff, because insns like sub.w or not.w
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can do a better job. */
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/* Determine if the upper half can be taken care of in no more
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than two bytes. */
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upper_half_easy_p = ((code != IOR && w1 == 0xffff)
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|| (code == AND && w1 == 0xff00));
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}
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/* Check if doing everything with one insn is no worse than
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using multiple insns. */
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if ((TARGET_H8300H || TARGET_H8300S)
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&& ((det & 0x0000ffff) != 0)
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&& ((det & 0xffff0000) != 0)
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&& (code == IOR || det != 0xffffff00)
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&& (code == IOR || det != 0xffff00ff)
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&& !(code == AND
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&& (det == 0xff00ffff
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|| (det & 0xffff00ff) == 0xff000000
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|| (det & 0xffffff00) == 0xff000000)))
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&& w0 != 0 && w1 != 0
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&& !(lower_half_easy_p && upper_half_easy_p))
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{
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sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
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output_asm_insn (insn_buf, operands);
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@ -2214,6 +2226,13 @@ compute_logical_op_length (mode, operands)
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/* The determinant of the algorithm. If we perform an AND, 0
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affects a bit. Otherwise, 1 affects a bit. */
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const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
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/* Break up DET into pieces. */
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const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
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const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
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const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
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const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
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int lower_half_easy_p = 0;
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int upper_half_easy_p = 0;
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/* Insn length. */
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unsigned int length = 0;
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@ -2242,20 +2261,25 @@ compute_logical_op_length (mode, operands)
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}
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break;
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case SImode:
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/* First, see if we can finish with one insn.
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if (TARGET_H8300H || TARGET_H8300S)
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{
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/* Determine if the lower half can be taken care of in no more
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than two bytes. */
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lower_half_easy_p = (b0 == 0
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|| b1 == 0
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|| (code != IOR && w0 == 0xffff));
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If code is either AND or XOR, we exclude two special cases,
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0xffffff00 and 0xffff00ff, because insns like sub.w or not.w
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can do a better job. */
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/* Determine if the upper half can be taken care of in no more
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than two bytes. */
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upper_half_easy_p = ((code != IOR && w1 == 0xffff)
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|| (code == AND && w1 == 0xff00));
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}
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/* Check if doing everything with one insn is no worse than
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using multiple insns. */
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if ((TARGET_H8300H || TARGET_H8300S)
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&& ((det & 0x0000ffff) != 0)
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&& ((det & 0xffff0000) != 0)
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&& (code == IOR || det != 0xffffff00)
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&& (code == IOR || det != 0xffff00ff)
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&& !(code == AND
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&& (det == 0xff00ffff
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|| (det & 0xffff00ff) == 0xff000000
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|| (det & 0xffffff00) == 0xff000000)))
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&& w0 != 0 && w1 != 0
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&& !(lower_half_easy_p && upper_half_easy_p))
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{
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if (REG_P (operands[2]))
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length += 4;
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@ -2336,6 +2360,13 @@ compute_logical_op_cc (mode, operands)
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/* The determinant of the algorithm. If we perform an AND, 0
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affects a bit. Otherwise, 1 affects a bit. */
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const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
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/* Break up DET into pieces. */
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const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
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const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
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const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
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const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
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int lower_half_easy_p = 0;
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int upper_half_easy_p = 0;
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/* Condition code. */
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enum attr_cc cc = CC_CLOBBER;
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@ -2351,20 +2382,25 @@ compute_logical_op_cc (mode, operands)
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}
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break;
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case SImode:
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/* First, see if we can finish with one insn.
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if (TARGET_H8300H || TARGET_H8300S)
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{
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/* Determine if the lower half can be taken care of in no more
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than two bytes. */
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lower_half_easy_p = (b0 == 0
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|| b1 == 0
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|| (code != IOR && w0 == 0xffff));
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If code is either AND or XOR, we exclude two special cases,
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0xffffff00 and 0xffff00ff, because insns like sub.w or not.w
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can do a better job. */
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/* Determine if the upper half can be taken care of in no more
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than two bytes. */
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upper_half_easy_p = ((code != IOR && w1 == 0xffff)
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|| (code == AND && w1 == 0xff00));
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}
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/* Check if doing everything with one insn is no worse than
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using multiple insns. */
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if ((TARGET_H8300H || TARGET_H8300S)
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&& ((det & 0x0000ffff) != 0)
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&& ((det & 0xffff0000) != 0)
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&& (code == IOR || det != 0xffffff00)
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&& (code == IOR || det != 0xffff00ff)
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&& !(code == AND
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&& (det == 0xff00ffff
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|| (det & 0xffff00ff) == 0xff000000
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|| (det & 0xffffff00) == 0xff000000)))
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&& w0 != 0 && w1 != 0
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&& !(lower_half_easy_p && upper_half_easy_p))
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{
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cc = CC_SET_ZNV;
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}
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