Vector support: rtx and mode definitions
From-SVN: r34677
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
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commit
f9f27ee563
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@ -1,3 +1,18 @@
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2000-06-24 Bernd Schmidt <bernds@cygnus.co.uk>
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* rtl.texi (Vector Operations): New node.
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(Arithmetic): Add ss_plus, us_plus, ss_minus, us_minus.
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(Conversions): Add ss_truncate, us_truncate.
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* rtl.def (VEC_MERGE, VEC_SELECT, VEC_CONCAT, VEC_REORDER,
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VEC_CONST, VEC_DUPLICATE, SS_PLUS, SS_MINUS, SS_TRUNCATE,
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US_TRUNCATE): New rtx codes.
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* machmode.def: Add vector modes.
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* machmode.h (enum mode_class): Add MODE_VECTOR_INT and
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MODE_VECTOR_FLOAT.
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(INTEGER_MODE_P): Check for MODE_VECTOR_INT.
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(FLOAT_MODE_P): Check for MODE_VECTOR_FLOAT.
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(VECTOR_MODE_P): New.
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2000-06-24 Nathan Sidwell <nathan@codesourcery.com>
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* cpp.texi: Clarify #pragma GCC namespace.
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@ -45,6 +45,7 @@ Boston, MA 02111-1307, USA. */
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MODE_PARTIAL_INT - PQImode, PHImode, PSImode and PDImode
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MODE_CC - modes used for representing the condition code in a register
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MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT - complex number
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MODE_VECTOR_INT, MODE_VECTOR_FLOAT - vector
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MODE_RANDOM - anything else
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Fourth argument is the relative size of the object, in bytes.
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@ -100,6 +101,33 @@ DEF_MACHMODE (CDImode, "CDI", MODE_COMPLEX_INT, 16, 8, CTImode)
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DEF_MACHMODE (CTImode, "CTI", MODE_COMPLEX_INT, 32, 16, COImode)
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DEF_MACHMODE (COImode, "COI", MODE_COMPLEX_INT, 64, 32, VOIDmode)
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/* Vector modes. */
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/* There are no V1xx vector modes. These are equivalent to normal non-vector
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modes. */
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DEF_MACHMODE (V2QImode, "V2QI", MODE_VECTOR_INT, 2, 1, VOIDmode)
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DEF_MACHMODE (V2HImode, "V2HI", MODE_VECTOR_INT, 4, 2, VOIDmode)
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DEF_MACHMODE (V2SImode, "V2SI", MODE_VECTOR_INT, 8, 4, VOIDmode)
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DEF_MACHMODE (V2DImode, "V2DI", MODE_VECTOR_INT, 16, 8, VOIDmode)
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DEF_MACHMODE (V4QImode, "V4QI", MODE_VECTOR_INT, 4, 1, VOIDmode)
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DEF_MACHMODE (V4HImode, "V4HI", MODE_VECTOR_INT, 8, 2, VOIDmode)
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DEF_MACHMODE (V4SImode, "V4SI", MODE_VECTOR_INT, 16, 4, VOIDmode)
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DEF_MACHMODE (V4DImode, "V4DI", MODE_VECTOR_INT, 32, 8, VOIDmode)
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DEF_MACHMODE (V8QImode, "V8QI", MODE_VECTOR_INT, 8, 1, VOIDmode)
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DEF_MACHMODE (V8HImode, "V8HI", MODE_VECTOR_INT, 16, 2, VOIDmode)
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DEF_MACHMODE (V8SImode, "V8SI", MODE_VECTOR_INT, 32, 4, VOIDmode)
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DEF_MACHMODE (V8DImode, "V8DI", MODE_VECTOR_INT, 64, 8, VOIDmode)
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DEF_MACHMODE (V2SFmode, "V2SF", MODE_VECTOR_FLOAT, 8, 4, VOIDmode)
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DEF_MACHMODE (V2DFmode, "V2DF", MODE_VECTOR_FLOAT, 16, 8, VOIDmode)
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DEF_MACHMODE (V4SFmode, "V4SF", MODE_VECTOR_FLOAT, 16, 4, VOIDmode)
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DEF_MACHMODE (V4DFmode, "V4DF", MODE_VECTOR_FLOAT, 32, 8, VOIDmode)
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DEF_MACHMODE (V8SFmode, "V8SF", MODE_VECTOR_FLOAT, 32, 4, VOIDmode)
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DEF_MACHMODE (V8DFmode, "V8DF", MODE_VECTOR_FLOAT, 64, 8, VOIDmode)
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/* BLKmode is used for structures, arrays, etc.
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that fit no more specific mode. */
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DEF_MACHMODE (BLKmode, "BLK", MODE_RANDOM, 0, 0, VOIDmode)
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@ -42,7 +42,9 @@ extern const char * const mode_name[];
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#define GET_MODE_NAME(MODE) (mode_name[(int) (MODE)])
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enum mode_class { MODE_RANDOM, MODE_INT, MODE_FLOAT, MODE_PARTIAL_INT, MODE_CC,
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MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT, MAX_MODE_CLASS};
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MODE_COMPLEX_INT, MODE_COMPLEX_FLOAT,
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MODE_VECTOR_INT, MODE_VECTOR_FLOAT,
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MAX_MODE_CLASS};
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/* Get the general kind of object that mode MODE represents
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(integer, floating, complex, etc.) */
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@ -54,18 +56,25 @@ extern const enum mode_class mode_class[];
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#define INTEGRAL_MODE_P(MODE) \
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(GET_MODE_CLASS (MODE) == MODE_INT \
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|| GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT \
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT)
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT \
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|| GET_MODE_CLASS (MODE) == MODE_VECTOR_INT)
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/* Nonzero if MODE is a floating-point mode. */
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#define FLOAT_MODE_P(MODE) \
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(GET_MODE_CLASS (MODE) == MODE_FLOAT \
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
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|| GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)
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/* Nonzero if MODE is a complex mode. */
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#define COMPLEX_MODE_P(MODE) \
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(GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT \
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
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/* Nonzero if MODE is a vector mode. */
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#define VECTOR_MODE_P(MODE) \
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(GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
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|| GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)
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/* Get the size in bytes of an object of mode MODE. */
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extern const unsigned int mode_size[];
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46
gcc/rtl.def
46
gcc/rtl.def
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@ -928,6 +928,52 @@ DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
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tree-based optimizations once front-end conversions are complete. */
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DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
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/* Describes a merge operation between two vector values.
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Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
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that specifies where the parts of the result are taken from. Set bits
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indicate operand 0, clear bits indicate operand 1. The parts are defined
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by the mode of the vectors. */
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DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
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/* Describes an operation that selects parts of a vector.
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Operands 0 is the source vector, operand 1 is a PARALLEL that contains
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a CONST_INT for each of the subparts of the result vector, giving the
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number of the source subpart that should be stored into it. */
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DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
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/* Describes a vector concat operation. Operands 0 and 1 are the source
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vectors, the result is a vector that is as long as operands 0 and 1
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combined and is the concatenation of the two source vectors. */
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DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
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/* Describes a vector constant. Each part of the PARALLEL that is operand 0
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describes a constant for one of the subparts. */
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DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x')
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/* Describes an operation that converts a small vector into a larger one by
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duplicating the input values. The output vector mode must have the same
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submodes as the input vector mode, and the number of output parts must be
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an integer multiple of the number of input parts. */
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DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
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/* Addition with signed saturation */
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DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
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/* Addition with unsigned saturation */
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DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
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/* Operand 0 minus operand 1, with signed saturation. */
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DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
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/* Operand 0 minus operand 1, with unsigned saturation. */
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DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
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/* Signed saturating truncate. */
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DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
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/* Unsigned saturating truncate. */
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DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
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/* The SSA phi operator.
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The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
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85
gcc/rtl.texi
85
gcc/rtl.texi
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@ -29,6 +29,7 @@ form uses nested parentheses to indicate the pointers in the internal form.
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* Arithmetic:: Expressions representing arithmetic on other expressions.
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* Comparisons:: Expressions representing comparison of expressions.
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* Bit Fields:: Expressions representing bitfields in memory or reg.
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* Vector Operations:: Expressions involving vector datatypes.
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* Conversions:: Extending, truncating, floating or fixing.
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* RTL Declarations:: Declaring volatility, constancy, etc.
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* Side Effects:: Expressions for storing in registers, etc.
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@ -1347,6 +1348,30 @@ item minus the number of bits set by the @code{high} code
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@item (minus:@var{m} @var{x} @var{y})
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Like @code{plus} but represents subtraction.
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@findex ss_plus
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@cindex RTL addition with signed saturation
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@item (ss_plus:@var{m} @var{x} @var{y})
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Like @code{plus}, but using signed saturation in case of an overflow.
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@findex us_plus
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@cindex RTL addition with unsigned saturation
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@item (us_plus:@var{m} @var{x} @var{y})
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Like @code{plus}, but using unsigned saturation in case of an overflow.
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@findex ss_minus
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@cindex RTL addition with signed saturation
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@item (ss_minus:@var{m} @var{x} @var{y})
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Like @code{minus}, but using signed saturation in case of an overflow.
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@findex us_minus
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@cindex RTL addition with unsigned saturation
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@item (us_minus:@var{m} @var{x} @var{y})
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Like @code{minus}, but using unsigned saturation in case of an overflow.
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@findex compare
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@cindex RTL comparison
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@item (compare:@var{m} @var{x} @var{y})
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@ -1695,6 +1720,52 @@ bit field. The same sequence of bits are extracted, but they
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are filled to an entire word with zeros instead of by sign-extension.
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@end table
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@node Vector Operations
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@section Vector Operations
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@cindex vector operations
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All normal rtl expressions can be used with vector modes; they are
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interpreted as operating on each part of the vector independently.
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Additionally, there are a few new expressions to describe specific vector
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operations.
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@table @code
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@findex vec_merge
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@item (vec_merge:@var{m} @var{vec1} @var{vec2} @var{items})
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This describes a merge operation between two vectors. The result is a vector
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of mode @var{m}; its elements are selected from either @var{vec1} or
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@var{vec2}. Which elements are selected is described by @var{items}, which
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is a bit mask represented by a @code{const_int}; a zero bit indicates the
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corresponding element in the result vector is taken from @var{vec2} while
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a set bit indicates it is taken from @var{vec1}.
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@findex vec_select
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@item (vec_select:@var{m} @var{vec1} @var{selection})
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This describes an operation that selects parts of a vector. @var{vec1} is
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the source vector, @var{selection} is a @code{parallel} that contains a
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@code{const_int} for each of the subparts of the result vector, giving the
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number of the source subpart that should be stored into it.
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@findex vec_concat
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@item (vec_concat:@var{m} @var{vec1} @var{vec2})
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Describes a vector concat operation. The result is a concatenation of the
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vectors @var{vec1} and @var{vec2}; its length is the sum of the lengths of
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the two inputs.
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@findex vec_const
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@item (vec_const:@var{m} @var{subparts})
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This describes a constant vector. @var{subparts} is a @code{parallel} that
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contains a constant for each of the subparts of the vector.
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@findex vec_duplicate
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@item (vec_duplicate:@var{m} @var{vec})
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This operation converts a small vector into a larger one by duplicating the
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input values. The output vector mode must have the same submodes as the
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input vector mode, and the number of output parts must be an integer multiple
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of the number of input parts.
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@end table
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@node Conversions
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@section Conversions
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@cindex conversions
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@ -1747,6 +1818,20 @@ Represents the result of truncating the value @var{x}
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to machine mode @var{m}. @var{m} must be a fixed-point mode
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and @var{x} a fixed-point value of a mode wider than @var{m}.
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@findex ss_truncate
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@item (ss_truncate:@var{m} @var{x})
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Represents the result of truncating the value @var{x}
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to machine mode @var{m}, using signed saturation in the case of
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overflow. Both @var{m} and the mode of @var{x} must be fixed-point
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modes.
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@findex us_truncate
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@item (us_truncate:@var{m} @var{x})
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Represents the result of truncating the value @var{x}
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to machine mode @var{m}, using unsigned saturation in the case of
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overflow. Both @var{m} and the mode of @var{x} must be fixed-point
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modes.
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@findex float_truncate
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@item (float_truncate:@var{m} @var{x})
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Represents the result of truncating the value @var{x}
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