config.gcc (powerpc*-*-*): Add new cores e300c2 and e300c3.
2008-02-21 Edmar Wienskoski <edmar@freescale.com>
* config.gcc (powerpc*-*-*): Add new cores e300c2 and e300c3.
* config/rs6000/e300c2c3.md: New file.
* config/rs6000/rs6000.c (processor_costs): Add new costs for
e300c2 and e300c3.
(rs6000_override_options): Add e300c2 and e300c3 cases to
processor_target_table. Do not allow usage of Altivec or Spe
with e300 cores. Initialize rs6000_cost for e300c2 and e300c3.
(rs6000_issue_rate): Set issue rate for e300c2 and e300c3.
* config/rs6000/rs6000.h (processor_type): Add
PROCESSOR_PPCE300C2 and PROCESSOR_PPCE300C3.
(ASM_CPU_SPEC): Add e300c2 and e300c3.
* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce300c2
and ppce300c3. Include e300c2c3.md.
From-SVN: r132589
This commit is contained in:
Edmar Wienskoski
David Edelsohn
parent
a94caabf5a
commit
fa41c30597
@ -1,3 +1,19 @@
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2008-02-21 Edmar Wienskoski <edmar@freescale.com>
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* config.gcc (powerpc*-*-*): Add new cores e300c2 and e300c3.
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* config/rs6000/e300c2c3.md: New file.
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* config/rs6000/rs6000.c (processor_costs): Add new costs for
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e300c2 and e300c3.
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(rs6000_override_options): Add e300c2 and e300c3 cases to
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processor_target_table. Do not allow usage of Altivec or Spe
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with e300 cores. Initialize rs6000_cost for e300c2 and e300c3.
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(rs6000_issue_rate): Set issue rate for e300c2 and e300c3.
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* config/rs6000/rs6000.h (processor_type): Add
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PROCESSOR_PPCE300C2 and PROCESSOR_PPCE300C3.
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(ASM_CPU_SPEC): Add e300c2 and e300c3.
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* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce300c2
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and ppce300c3. Include e300c2c3.md.
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2008-02-23 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.h (CONSTANT_ALIGNMENT): Use STRICT_ALIGNMENT
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@ -3130,7 +3130,7 @@ case "${target}" in
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| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
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| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
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| 601 | 602 | 603 | 603e | ec603e | 604 \
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| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
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| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
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| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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# OK
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;;
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189
gcc/config/rs6000/e300c2c3.md
Normal file
189
gcc/config/rs6000/e300c2c3.md
Normal file
@ -0,0 +1,189 @@
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;; Pipeline description for Motorola PowerPC e300c3 core.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
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(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
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;; We don't simulate general issue queue (GIC). If we have SU insn
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;; and then SU1 insn, they can not be issued on the same cycle
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;; (although SU1 insn and then SU insn can be issued) because the SU
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;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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;; multipass insn scheduling will find the situation and issue the SU1
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;; insn and then the SU insn.
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(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
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;; We could describe completion buffers slots in combination with the
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;; retirement units and the order of completion but the result
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;; automaton would behave in the same way because we can not describe
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;; real latency time with taking in order completion into account.
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;; Actually we could define the real latency time by querying reserved
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;; automaton units but the current scheduler uses latency time before
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;; issuing insns and making any reservations.
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;;
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;; So our description is aimed to achieve a insn schedule in which the
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;; insns would not wait in the completion buffer.
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(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
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;; Branch unit:
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(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
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;; IU:
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(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
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;; IU: This used to describe non-pipelined division.
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(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
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;; SRU:
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(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
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;; Here we simplified LSU unit description not describing the stages.
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(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
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;; FPU:
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(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
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;; The following units are used to make automata deterministic
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(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
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(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
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(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
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(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
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(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
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(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
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(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
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;; Some useful abbreviations.
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(define_reservation "ppce300c3_decode"
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"ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
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(define_reservation "ppce300c3_issue"
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"ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
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(define_reservation "ppce300c3_retire"
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"ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
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(define_reservation "ppce300c3_iu_stage0"
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"ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
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;; Compares can be executed either one of the IU or SRU
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(define_insn_reservation "ppce300c3_cmp" 1
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(and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
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+ppce300c3_retire")
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;; Other one cycle IU insns
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(define_insn_reservation "ppce300c3_iu" 1
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(and (eq_attr "type" "integer,insert_word")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
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;; Branch. Actually this latency time is not used by the scheduler.
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(define_insn_reservation "ppce300c3_branch" 1
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(and (eq_attr "type" "jmpreg,branch")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
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;; Multiply is non-pipelined but can be executed in any IU
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(define_insn_reservation "ppce300c3_multiply" 2
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
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ppce300c3_iu_stage0+ppce300c3_retire")
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;; Divide. We use the average latency time here. We omit reserving a
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;; retire unit because of the result automata will be huge.
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(define_insn_reservation "ppce300c3_divide" 20
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(and (eq_attr "type" "idiv")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
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ppce300c3_mu_div*19")
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;; CR logical
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(define_insn_reservation "ppce300c3_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mfcr
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(define_insn_reservation "ppce300c3_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mtcrf
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(define_insn_reservation "ppce300c3_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mtjmpr
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(define_insn_reservation "ppce300c3_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Float point instructions
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(define_insn_reservation "ppce300c3_fpcompare" 3
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fp" 3
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_dmul" 4
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
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; Divides are not pipelined
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(define_insn_reservation "ppce300c3_sdiv" 18
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
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(define_insn_reservation "ppce300c3_ddiv" 33
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
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;; Loads
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(define_insn_reservation "ppce300c3_load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fpload" 2
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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;; Stores.
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(define_insn_reservation "ppce300c3_store" 2
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(and (eq_attr "type" "store,store_ux,store_u")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fpstore" 2
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(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = {
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1, /* prefetch streams /*/
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};
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/* Instruction costs on E300C2 and E300C3 cores. */
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static const
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struct processor_costs ppce300c2c3_cost = {
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COSTS_N_INSNS (4), /* mulsi */
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COSTS_N_INSNS (4), /* mulsi_const */
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COSTS_N_INSNS (4), /* mulsi_const9 */
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COSTS_N_INSNS (4), /* muldi */
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COSTS_N_INSNS (19), /* divsi */
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COSTS_N_INSNS (19), /* divdi */
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COSTS_N_INSNS (3), /* fp */
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COSTS_N_INSNS (4), /* dmul */
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COSTS_N_INSNS (18), /* sdiv */
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COSTS_N_INSNS (33), /* ddiv */
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};
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/* Instruction costs on POWER4 and POWER5 processors. */
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static const
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struct processor_costs power4_cost = {
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@ -1420,6 +1435,8 @@ rs6000_override_options (const char *default_cpu)
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{"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
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/* 8548 has a dummy entry for now. */
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{"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
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{"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
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{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"970", PROCESSOR_POWER4,
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POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
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@ -1526,6 +1543,14 @@ rs6000_override_options (const char *default_cpu)
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if (TARGET_E500)
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rs6000_isel = 1;
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if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3)
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{
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if (TARGET_ALTIVEC)
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error ("AltiVec not supported in this target");
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if (TARGET_SPE)
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error ("Spe not supported in this target");
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}
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/* If we are optimizing big endian systems for space, use the load/store
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multiple and string instructions. */
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if (BYTES_BIG_ENDIAN && optimize_size)
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@ -1845,6 +1870,11 @@ rs6000_override_options (const char *default_cpu)
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rs6000_cost = &ppc8540_cost;
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break;
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case PROCESSOR_PPCE300C2:
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case PROCESSOR_PPCE300C3:
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rs6000_cost = &ppce300c2c3_cost;
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break;
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case PROCESSOR_POWER4:
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case PROCESSOR_POWER5:
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rs6000_cost = &power4_cost;
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@ -18527,6 +18557,8 @@ rs6000_issue_rate (void)
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case CPU_PPC7400:
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case CPU_PPC8540:
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case CPU_CELL:
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case CPU_PPCE300C2:
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case CPU_PPCE300C3:
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return 2;
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case CPU_RIOS2:
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case CPU_PPC604:
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@ -117,6 +117,8 @@
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%{mcpu=G5: -mpower4 -maltivec} \
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%{mcpu=8540: -me500} \
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%{mcpu=8548: -me500} \
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%{mcpu=e300c2: -me300} \
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%{mcpu=e300c3: -me300} \
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%{maltivec: -maltivec} \
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-many"
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@ -262,6 +264,8 @@ enum processor_type
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PROCESSOR_PPC7400,
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PROCESSOR_PPC7450,
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PROCESSOR_PPC8540,
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PROCESSOR_PPCE300C2,
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PROCESSOR_PPCE300C3,
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PROCESSOR_POWER4,
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PROCESSOR_POWER5,
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PROCESSOR_POWER6,
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@ -133,7 +133,7 @@
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in rs6000.h.
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(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
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(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell"
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(const (symbol_ref "rs6000_cpu_attr")))
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@ -166,6 +166,7 @@
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(include "7xx.md")
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(include "7450.md")
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(include "8540.md")
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(include "e300c2c3.md")
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(include "power4.md")
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(include "power5.md")
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(include "power6.md")
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|
||||
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