[arm] Early split addvdi4
This patch adds early splitting for addvdi4; it's very similar to the uaddvdi4 splitter, but the details are just different enough in places, especially for the patterns that match the splitting, where we have to compare against the non-widened version to detect if overflow occurred. I've also added a testcase to the testsuite for a couple of constants that caught me out during the development of this patch. They're probably arm-specific values, but the test is generic enough that I've included it for all targets. [gcc] * config/arm/arm.c (arm_select_cc_mode): Allow either the first or second operand of the PLUS inside a DImode equality test to be sign-extend when selecting CC_Vmode. * config/arm/arm.md (addvdi4): Early-split the operation into SImode instructions. (addsi3_cin_vout_reg, addsi3_cin_vout_imm, addsi3_cin_vout_0): New expand patterns. (addsi3_cin_vout_reg_insn, addsi3_cin_vout_imm_insn): New patterns. (addsi3_cin_vout_0): Likewise. (adddi3_compareV): Delete. [gcc/testsuite] * gcc.dg/builtin-arith-overflow-3.c: New test. From-SVN: r277186
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
db962d0ad4
commit
fa62df0e60
@ -1,3 +1,16 @@
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.c (arm_select_cc_mode): Allow either the first
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or second operand of the PLUS inside a DImode equality test to be
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sign-extend when selecting CC_Vmode.
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* config/arm/arm.md (addvdi4): Early-split the operation into SImode
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instructions.
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(addsi3_cin_vout_reg, addsi3_cin_vout_imm, addsi3_cin_vout_0): New
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expand patterns.
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(addsi3_cin_vout_reg_insn, addsi3_cin_vout_imm_insn): New patterns.
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(addsi3_cin_vout_0): Likewise.
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(adddi3_compareV): Delete.
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.md (addsi3_compareV_reg_nosum): New insn.
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@ -15414,7 +15414,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
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if (GET_MODE (x) == DImode
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&& (op == EQ || op == NE)
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&& GET_CODE (x) == PLUS
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&& GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
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&& (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
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|| GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
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&& GET_CODE (y) == SIGN_EXTEND
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&& GET_CODE (XEXP (y, 0)) == PLUS)
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return CC_Vmode;
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@ -505,18 +505,173 @@
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})
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(define_expand "addvdi4"
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[(match_operand:DI 0 "register_operand")
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(match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "register_operand")
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[(match_operand:DI 0 "s_register_operand")
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(match_operand:DI 1 "s_register_operand")
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(match_operand:DI 2 "reg_or_int_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_adddi3_compareV (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
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rtx lo_result, hi_result;
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rtx lo_op1, hi_op1, lo_op2, hi_op2;
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arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
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&lo_op2, &hi_op2);
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lo_result = gen_lowpart (SImode, operands[0]);
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hi_result = gen_highpart (SImode, operands[0]);
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if (lo_op2 == const0_rtx)
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{
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emit_move_insn (lo_result, lo_op1);
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if (!arm_add_operand (hi_op2, SImode))
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hi_op2 = force_reg (SImode, hi_op2);
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emit_insn (gen_addvsi4 (hi_result, hi_op1, hi_op2, operands[3]));
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}
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else
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{
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if (!arm_add_operand (lo_op2, SImode))
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lo_op2 = force_reg (SImode, lo_op2);
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if (!arm_not_operand (hi_op2, SImode))
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hi_op2 = force_reg (SImode, hi_op2);
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emit_insn (gen_addsi3_compare_op1 (lo_result, lo_op1, lo_op2));
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if (hi_op2 == const0_rtx)
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emit_insn (gen_addsi3_cin_vout_0 (hi_result, hi_op1));
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else if (CONST_INT_P (hi_op2))
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emit_insn (gen_addsi3_cin_vout_imm (hi_result, hi_op1, hi_op2));
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else
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emit_insn (gen_addsi3_cin_vout_reg (hi_result, hi_op1, hi_op2));
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arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
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}
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DONE;
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})
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(define_expand "addsi3_cin_vout_reg"
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[(parallel
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[(set (match_dup 3)
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(compare:CC_V
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(plus:DI
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(plus:DI (match_dup 4)
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(sign_extend:DI (match_operand:SI 1 "s_register_operand")))
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(sign_extend:DI (match_operand:SI 2 "s_register_operand")))
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(sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
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(match_dup 2)))))
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(set (match_operand:SI 0 "s_register_operand")
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(plus:SI (plus:SI (match_dup 5) (match_dup 1))
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(match_dup 2)))])]
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"TARGET_32BIT"
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{
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operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
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rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
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operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
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operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
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}
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)
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(define_insn "*addsi3_cin_vout_reg_insn"
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[(set (reg:CC_V CC_REGNUM)
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(compare:CC_V
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(plus:DI
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(plus:DI
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(match_operand:DI 3 "arm_carry_operation" "")
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")))
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
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(sign_extend:DI
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(plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
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(match_dup 1))
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(match_dup 2)))))
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(set (match_operand:SI 0 "s_register_operand" "=l,r")
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(plus:SI (plus:SI (match_dup 4) (match_dup 1))
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(match_dup 2)))]
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"TARGET_32BIT"
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"@
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adcs%?\\t%0, %0, %2
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adcs%?\\t%0, %1, %2"
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[(set_attr "type" "alus_sreg")
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(set_attr "arch" "t2,*")
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(set_attr "length" "2,4")]
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)
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(define_expand "addsi3_cin_vout_imm"
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[(parallel
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[(set (match_dup 3)
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(compare:CC_V
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(plus:DI
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(plus:DI (match_dup 4)
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(sign_extend:DI (match_operand:SI 1 "s_register_operand")))
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(match_dup 2))
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(sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
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(match_dup 2)))))
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(set (match_operand:SI 0 "s_register_operand")
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(plus:SI (plus:SI (match_dup 5) (match_dup 1))
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(match_operand 2 "arm_adcimm_operand")))])]
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"TARGET_32BIT"
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{
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operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
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rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
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operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
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operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
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}
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)
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(define_insn "*addsi3_cin_vout_imm_insn"
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[(set (reg:CC_V CC_REGNUM)
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(compare:CC_V
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(plus:DI
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(plus:DI
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(match_operand:DI 3 "arm_carry_operation" "")
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")))
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(match_operand 2 "arm_adcimm_operand" "I,K"))
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(sign_extend:DI
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(plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
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(match_dup 1))
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(match_dup 2)))))
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(plus:SI (plus:SI (match_dup 4) (match_dup 1))
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(match_dup 2)))]
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"TARGET_32BIT"
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"@
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adcs%?\\t%0, %1, %2
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sbcs%?\\t%0, %1, #%B2"
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[(set_attr "type" "alus_imm")]
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)
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(define_expand "addsi3_cin_vout_0"
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[(parallel
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[(set (match_dup 2)
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(compare:CC_V
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(plus:DI (match_dup 3)
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(sign_extend:DI (match_operand:SI 1 "s_register_operand")))
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(sign_extend:DI (plus:SI (match_dup 4) (match_dup 1)))))
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(set (match_operand:SI 0 "s_register_operand")
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(plus:SI (match_dup 4) (match_dup 1)))])]
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"TARGET_32BIT"
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{
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operands[2] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
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rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
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operands[3] = gen_rtx_LTU (DImode, ccin, const0_rtx);
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operands[4] = gen_rtx_LTU (SImode, ccin, const0_rtx);
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}
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)
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(define_insn "*addsi3_cin_vout_0_insn"
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[(set (reg:CC_V CC_REGNUM)
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(compare:CC_V
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(plus:DI
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(match_operand:DI 2 "arm_carry_operation" "")
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))
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(sign_extend:DI (plus:SI
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(match_operand:SI 3 "arm_carry_operation" "")
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(match_dup 1)))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 3) (match_dup 1)))]
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"TARGET_32BIT"
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"adcs%?\\t%0, %1, #0"
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[(set_attr "type" "alus_imm")]
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)
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(define_expand "uaddvsi4"
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[(match_operand:SI 0 "s_register_operand")
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(match_operand:SI 1 "s_register_operand")
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@ -770,22 +925,6 @@
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]
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)
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(define_insn "adddi3_compareV"
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[(set (reg:CC_V CC_REGNUM)
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(ne:CC_V
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(plus:TI
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(sign_extend:TI (match_operand:DI 1 "s_register_operand" "r"))
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(sign_extend:TI (match_operand:DI 2 "s_register_operand" "r")))
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(sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
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(set (match_operand:DI 0 "s_register_operand" "=&r")
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(plus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"adds\\t%Q0, %Q1, %Q2;adcs\\t%R0, %R1, %R2"
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[(set_attr "conds" "set")
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(set_attr "length" "8")
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(set_attr "type" "multiple")]
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)
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(define_insn "addsi3_compareV_reg"
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[(set (reg:CC_V CC_REGNUM)
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(compare:CC_V
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@ -1,3 +1,7 @@
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* gcc.dg/builtin-arith-overflow-3.c: New test.
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* gcc.target/arm/negdi-3.c: Remove XFAIL markers.
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41
gcc/testsuite/gcc.dg/builtin-arith-overflow-3.c
Normal file
41
gcc/testsuite/gcc.dg/builtin-arith-overflow-3.c
Normal file
@ -0,0 +1,41 @@
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/* { dg-do run } */
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/* { dg-options "-O2" } */
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static int cnt = 0;
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#define LL_MIN ((long long)(-__LONG_LONG_MAX__ - 1))
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#define SC1 (LL_MIN + 5)
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#define UC1 ((1ULL << (__LONG_LONG_WIDTH__ - 1)) | 5ULL)
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#define UC2 (~UC1)
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long long __attribute__ ((noinline, noclone))
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f1 (long long a)
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{
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long long x;
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if (__builtin_add_overflow (a, SC1, &x)) cnt++;
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return x;
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}
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unsigned long long __attribute__ ((noinline, noclone))
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f2 (unsigned long long a)
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{
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unsigned long long x;
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if (__builtin_add_overflow (a, UC1, &x))
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cnt++;
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return x;
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}
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int main ()
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{
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if (f1 (-5) != LL_MIN) __builtin_abort ();
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if (cnt != 0) __builtin_abort ();
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f1 (-6);
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if (cnt != 1) __builtin_abort ();
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cnt = 0;
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if (f2 (UC2) != ~0ULL) __builtin_abort ();
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if (cnt != 0) __builtin_abort ();
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if (f2 (UC2 + 1) != 0) __builtin_abort ();
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if (cnt != 1) __builtin_abort ();
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return 0;
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}
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