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Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823) 

The pattern was generating zero-extended rather than sign-extended
CONST_INTs.

2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/91823
	* config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate
	canonical CONST_INTs.  Use gen_rtvec.

From-SVN: r276055
This commit is contained in:
Richard Sandiford 2019-09-23 11:56:47 +00:00 committed by Richard Sandiford
parent d469a71e5a
commit fa87544ca1
2 changed files with 8 additions and 7 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2019-09-23 Richard Sandiford <richard.sandiford@arm.com>
PR target/91823
* config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate
canonical CONST_INTs. Use gen_rtvec.
2019-09-23 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (get_initial_def_for_reduction): Simplify,

9
gcc/config/rs6000/altivec.md
View File

@ -2198,13 +2198,8 @@
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
rtx mask = gen_reg_rtx (V4SImode);
rtvec v = rtvec_alloc (4);
unsigned HOST_WIDE_INT mask_val = ((unsigned HOST_WIDE_INT)1) << 31;
RTVEC_ELT (v, 0) = GEN_INT (mask_val);
RTVEC_ELT (v, 1) = GEN_INT (mask_val);
RTVEC_ELT (v, 2) = GEN_INT (mask_val);
RTVEC_ELT (v, 3) = GEN_INT (mask_val);
rtx mask_val = gen_int_mode (HOST_WIDE_INT_1U << 31, SImode);
rtvec v = gen_rtvec (4, mask_val, mask_val, mask_val, mask_val);
emit_insn (gen_vec_initv4sisi (mask, gen_rtx_PARALLEL (V4SImode, v)));
emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],