diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7080815c770..5ecb9a48587 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-07-03 Andreas Schwab + + * config/ia64/ia64.md: Define new attribute "empty". + (prologue_use, nop_x, insn_group_barrier): Set it. + + * config/ia64/ia64.c (ia64_reorg): When looking for trailing call + skip over "empty" insns. + 2004-07-03 Richard Kenner * tree-inline.c (initialize_inlined_parameters): Pass proper function diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 783ebf747f5..e631e87cdda 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -7666,11 +7666,12 @@ ia64_reorg (void) insn = get_last_insn (); if (! INSN_P (insn)) insn = prev_active_insn (insn); - if (GET_CODE (insn) == INSN - && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE - && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) - { - saw_stop = 1; + /* Skip over insns that expand to nothing. */ + while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES) + { + if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE + && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) + saw_stop = 1; insn = prev_active_insn (insn); } if (GET_CODE (insn) == CALL_INSN) diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 07b6a612aae..b185bc82059 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -154,6 +154,10 @@ (define_attr "predicable" "no,yes" (const_string "yes")) +;; Empty. True iff this insn does not generate any code. + +(define_attr "empty" "no,yes" (const_string "no")) + ;; DFA descriptions of ia64 processors used for insn scheduling and @@ -5425,7 +5429,8 @@ "" "" [(set_attr "itanium_class" "ignore") - (set_attr "predicable" "no")]) + (set_attr "predicable" "no") + (set_attr "empty" "yes")]) ;; Allocate a new register frame. @@ -5592,7 +5597,8 @@ [(const_int 5)] "" "" - [(set_attr "itanium_class" "nop_x")]) + [(set_attr "itanium_class" "nop_x") + (set_attr "empty" "yes")]) ;; The following insn will be never generated. It is used only by ;; insn scheduler to change state before advancing cycle. @@ -5624,7 +5630,8 @@ "" ";;" [(set_attr "itanium_class" "stop_bit") - (set_attr "predicable" "no")]) + (set_attr "predicable" "no") + (set_attr "empty" "yes")]) (define_expand "trap" [(trap_if (const_int 1) (const_int 0))]