Add support for more sparc VIS 3.0 instructions.
gcc/ * config/sparc/sparc.md (UNSPEC_FHADD, UNSPEC_FHSUB, UNSPEC_XMUL): New unspecs. (muldi3_v8plus): Use output_v8plus_mult. (*naddsf3, *nadddf3, *nmulsf3, *nmuldf3, *nmuldf3_extend): New VIS 3.0 combiner patterns. (fhaddsf_vis, fhadddf_vis, fhsubsf_vis, fhsubdf_vis, fnhaddsf_vis, fnhaddf_vis, umulxhi_vis, *umulxhi_sp64, umulxhi_v8plus, xmulx_vis, *xmulx_sp64, xmulx_v8plus, xmulxhi_vis, *xmulxhi_sp64, xmulxhi_v8plus): New VIS 3.0 builtins patterns. * config/sparc/sparc.c (sparc_vis_init_builtins): Emit new builtins. (output_v8plus_mult): New function. * config/sparc/sparc-protos.h: Declare it. * config/sparc/visintrin.h (__vis_fhadds, __vis_fhaddd, __vis_fhsubs, __vis_fhsubd, __vis_fnhadds, __vis_fnhaddd, __vis_umulxhi, __vis_xmulx, __vis_xmulxhi): New intrinsics. * doc/extend.texi: Document new builtins. gcc/testsuite/ * gcc.target/sparc/fhalve.c: New test. * gcc.target/sparc/fnegop.c: New test. * gcc.target/sparc/xmul.c: New test. From-SVN: r179535
This commit is contained in:
David S. Miller
David S. Miller
parent
9a83cdf714
commit
facb3fd739
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@ -1,3 +1,24 @@
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2011-10-04 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.md (UNSPEC_FHADD, UNSPEC_FHSUB,
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UNSPEC_XMUL): New unspecs.
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(muldi3_v8plus): Use output_v8plus_mult.
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(*naddsf3, *nadddf3, *nmulsf3, *nmuldf3, *nmuldf3_extend):
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New VIS 3.0 combiner patterns.
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(fhaddsf_vis, fhadddf_vis, fhsubsf_vis, fhsubdf_vis,
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fnhaddsf_vis, fnhaddf_vis, umulxhi_vis, *umulxhi_sp64,
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umulxhi_v8plus, xmulx_vis, *xmulx_sp64, xmulx_v8plus,
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xmulxhi_vis, *xmulxhi_sp64, xmulxhi_v8plus): New VIS 3.0
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builtins patterns.
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* config/sparc/sparc.c (sparc_vis_init_builtins): Emit new
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builtins.
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(output_v8plus_mult): New function.
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* config/sparc/sparc-protos.h: Declare it.
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* config/sparc/visintrin.h (__vis_fhadds, __vis_fhaddd,
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__vis_fhsubs, __vis_fhsubd, __vis_fnhadds, __vis_fnhaddd,
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__vis_umulxhi, __vis_xmulx, __vis_xmulxhi): New intrinsics.
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* doc/extend.texi: Document new builtins.
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2011-10-04 Richard Henderson <rth@redhat.com>
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* c-typeck.c (c_build_vec_shuffle_expr): Fix uninitialized variable.
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@ -105,6 +105,7 @@ extern int v9_regcmp_p (enum rtx_code);
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extern int sparc_check_64 (rtx, rtx);
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extern rtx gen_df_reg (rtx, int);
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extern void sparc_expand_compare_and_swap_12 (rtx, rtx, rtx, rtx);
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extern const char *output_v8plus_mult (rtx, rtx *, const char *);
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#endif /* RTX_CODE */
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#endif /* __SPARC_PROTOS_H__ */
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@ -9236,6 +9236,12 @@ sparc_vis_init_builtins (void)
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void_type_node, 0);
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tree void_ftype_si = build_function_type_list (void_type_node,
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intSI_type_node, 0);
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tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
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float_type_node,
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float_type_node, 0);
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tree df_ftype_df_df = build_function_type_list (double_type_node,
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double_type_node,
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double_type_node, 0);
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/* Packing and expanding vectors. */
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def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
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@ -9552,6 +9558,26 @@ sparc_vis_init_builtins (void)
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def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
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si_ftype_v8qi_v8qi);
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}
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def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
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sf_ftype_sf_sf);
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def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
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df_ftype_df_df);
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def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
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sf_ftype_sf_sf);
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def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
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df_ftype_df_df);
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def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
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sf_ftype_sf_sf);
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def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
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df_ftype_df_df);
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def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
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di_ftype_di_di);
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def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
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di_ftype_di_di);
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def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
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di_ftype_di_di);
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}
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}
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@ -10738,4 +10764,77 @@ sparc_preferred_reload_class (rtx x, reg_class_t rclass)
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return rclass;
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}
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const char *
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output_v8plus_mult (rtx insn, rtx *operands, const char *name)
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{
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char mulstr[32];
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gcc_assert (! TARGET_ARCH64);
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if (sparc_check_64 (operands[1], insn) <= 0)
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output_asm_insn ("srl\t%L1, 0, %L1", operands);
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if (which_alternative == 1)
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output_asm_insn ("sllx\t%H1, 32, %H1", operands);
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (which_alternative == 1)
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{
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output_asm_insn ("or\t%L1, %H1, %H1", operands);
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sprintf (mulstr, "%s\t%%H1, %%2, %%L0", name);
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output_asm_insn (mulstr, operands);
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return "srlx\t%L0, 32, %H0";
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}
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else
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{
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output_asm_insn ("sllx\t%H1, 32, %3", operands);
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output_asm_insn ("or\t%L1, %3, %3", operands);
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sprintf (mulstr, "%s\t%%3, %%2, %%3", name);
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output_asm_insn (mulstr, operands);
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output_asm_insn ("srlx\t%3, 32, %H0", operands);
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return "mov\t%3, %L0";
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}
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}
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else if (rtx_equal_p (operands[1], operands[2]))
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{
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if (which_alternative == 1)
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{
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output_asm_insn ("or\t%L1, %H1, %H1", operands);
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sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", name);
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output_asm_insn (mulstr, operands);
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return "srlx\t%L0, 32, %H0";
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}
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else
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{
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output_asm_insn ("sllx\t%H1, 32, %3", operands);
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output_asm_insn ("or\t%L1, %3, %3", operands);
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sprintf (mulstr, "%s\t%%3, %%3, %%3", name);
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output_asm_insn (mulstr, operands);
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output_asm_insn ("srlx\t%3, 32, %H0", operands);
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return "mov\t%3, %L0";
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}
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}
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if (sparc_check_64 (operands[2], insn) <= 0)
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output_asm_insn ("srl\t%L2, 0, %L2", operands);
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if (which_alternative == 1)
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{
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output_asm_insn ("or\t%L1, %H1, %H1", operands);
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output_asm_insn ("sllx\t%H2, 32, %L1", operands);
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output_asm_insn ("or\t%L2, %L1, %L1", operands);
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sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", name);
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output_asm_insn (mulstr, operands);
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return "srlx\t%L0, 32, %H0";
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}
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else
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{
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output_asm_insn ("sllx\t%H1, 32, %3", operands);
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output_asm_insn ("sllx\t%H2, 32, %4", operands);
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output_asm_insn ("or\t%L1, %3, %3", operands);
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output_asm_insn ("or\t%L2, %4, %4", operands);
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sprintf (mulstr, "%s\t%%3, %%4, %%3", name);
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output_asm_insn (mulstr, operands);
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output_asm_insn ("srlx\t%3, 32, %H0", operands);
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return "mov\t%3, %L0";
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}
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}
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#include "gt-sparc.h"
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@ -86,6 +86,9 @@
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(UNSPEC_FCHKSM16 80)
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(UNSPEC_PDISTN 81)
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(UNSPEC_FUCMP 82)
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(UNSPEC_FHADD 83)
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(UNSPEC_FHSUB 84)
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(UNSPEC_XMUL 85)
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])
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(define_constants
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@ -4012,32 +4015,7 @@
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(clobber (match_scratch:SI 3 "=&h,X"))
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(clobber (match_scratch:SI 4 "=&h,X"))]
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"TARGET_V8PLUS"
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{
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if (sparc_check_64 (operands[1], insn) <= 0)
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output_asm_insn ("srl\t%L1, 0, %L1", operands);
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if (which_alternative == 1)
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output_asm_insn ("sllx\t%H1, 32, %H1", operands);
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (which_alternative == 1)
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return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0";
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else
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return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
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}
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else if (rtx_equal_p (operands[1], operands[2]))
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{
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if (which_alternative == 1)
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return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0";
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else
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return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
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}
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if (sparc_check_64 (operands[2], insn) <= 0)
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output_asm_insn ("srl\t%L2, 0, %L2", operands);
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if (which_alternative == 1)
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return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0";
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else
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return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
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}
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"* return output_v8plus_mult (insn, operands, \"mulx\");"
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[(set_attr "type" "multi")
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(set_attr "length" "9,8")])
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@ -8407,4 +8385,247 @@
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"TARGET_VIS3"
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"fucmp<code>8\t%1, %2, %0")
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(define_insn "*naddsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))))]
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"TARGET_VIS3"
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"fnadds\t%1, %2, %0"
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[(set_attr "type" "fp")])
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(define_insn "*nadddf3"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(neg:DF (plus:DF (match_operand:DF 1 "register_operand" "e")
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(match_operand:DF 2 "register_operand" "e"))))]
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"TARGET_VIS3"
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"fnaddd\t%1, %2, %0"
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[(set_attr "type" "fp")
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(set_attr "fptype" "double")])
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(define_insn "*nmulsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_VIS3"
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"fnmuls\t%1, %2, %0"
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[(set_attr "type" "fpmul")])
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(define_insn "*nmuldf3"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "e"))
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(match_operand:DF 2 "register_operand" "e")))]
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"TARGET_VIS3"
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"fnmuld\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "*nmuldf3_extend"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(mult:DF (neg:DF (float_extend:DF
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(match_operand:SF 1 "register_operand" "f")))
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(float_extend:DF
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(match_operand:SF 2 "register_operand" "f"))))]
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"TARGET_VIS3"
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"fnsmuld\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fhaddsf_vis"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")]
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UNSPEC_FHADD))]
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"TARGET_VIS3"
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"fhadds\t%1, %2, %0"
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[(set_attr "type" "fp")])
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(define_insn "fhadddf_vis"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")]
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UNSPEC_FHADD))]
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"TARGET_VIS3"
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"fhaddd\t%1, %2, %0"
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[(set_attr "type" "fp")
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(set_attr "fptype" "double")])
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(define_insn "fhsubsf_vis"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")]
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UNSPEC_FHSUB))]
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"TARGET_VIS3"
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"fhsubs\t%1, %2, %0"
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[(set_attr "type" "fp")])
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(define_insn "fhsubdf_vis"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")]
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UNSPEC_FHSUB))]
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"TARGET_VIS3"
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"fhsubd\t%1, %2, %0"
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[(set_attr "type" "fp")
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(set_attr "fptype" "double")])
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(define_insn "fnhaddsf_vis"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(neg:SF (unspec:SF [(match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")]
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UNSPEC_FHADD)))]
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"TARGET_VIS3"
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"fnhadds\t%1, %2, %0"
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[(set_attr "type" "fp")])
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(define_insn "fnhadddf_vis"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(neg:DF (unspec:DF [(match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")]
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UNSPEC_FHADD)))]
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"TARGET_VIS3"
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"fnhaddd\t%1, %2, %0"
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[(set_attr "type" "fp")
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(set_attr "fptype" "double")])
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(define_expand "umulxhi_vis"
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[(set (match_operand:DI 0 "register_operand" "")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (zero_extend:TI
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(match_operand:DI 1 "arith_operand" ""))
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(zero_extend:TI
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(match_operand:DI 2 "arith_operand" "")))
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(const_int 64))))]
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"TARGET_VIS3"
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{
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if (! TARGET_ARCH64)
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{
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emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2]));
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DONE;
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}
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})
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(define_insn "*umulxhi_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (zero_extend:TI
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(match_operand:DI 1 "arith_operand" "%r"))
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(zero_extend:TI
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(match_operand:DI 2 "arith_operand" "rI")))
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(const_int 64))))]
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"TARGET_VIS3 && TARGET_ARCH64"
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"umulxhi\t%1, %2, %0"
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[(set_attr "type" "imul")])
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(define_insn "umulxhi_v8plus"
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[(set (match_operand:DI 0 "register_operand" "=r,h")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" "%r,0"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" "rI,rI")))
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:SI 3 "=&h,X"))
|
||||
(clobber (match_scratch:SI 4 "=&h,X"))]
|
||||
"TARGET_VIS3 && ! TARGET_ARCH64"
|
||||
"* return output_v8plus_mult (insn, operands, \"umulxhi\");"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length" "9,8")])
|
||||
|
||||
(define_expand "xmulx_vis"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(truncate:DI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" ""))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" ""))]
|
||||
UNSPEC_XMUL)))]
|
||||
"TARGET_VIS3"
|
||||
{
|
||||
if (! TARGET_ARCH64)
|
||||
{
|
||||
emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2]));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
(define_insn "*xmulx_sp64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(truncate:DI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" "%r"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" "rI"))]
|
||||
UNSPEC_XMUL)))]
|
||||
"TARGET_VIS3 && TARGET_ARCH64"
|
||||
"xmulx\t%1, %2, %0"
|
||||
[(set_attr "type" "imul")])
|
||||
|
||||
(define_insn "xmulx_v8plus"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,h")
|
||||
(truncate:DI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" "%r,0"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" "rI,rI"))]
|
||||
UNSPEC_XMUL)))
|
||||
(clobber (match_scratch:SI 3 "=&h,X"))
|
||||
(clobber (match_scratch:SI 4 "=&h,X"))]
|
||||
"TARGET_VIS3 && ! TARGET_ARCH64"
|
||||
"* return output_v8plus_mult (insn, operands, \"xmulx\");"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length" "9,8")])
|
||||
|
||||
(define_expand "xmulxhi_vis"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" ""))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" ""))]
|
||||
UNSPEC_XMUL)
|
||||
(const_int 64))))]
|
||||
"TARGET_VIS3"
|
||||
{
|
||||
if (! TARGET_ARCH64)
|
||||
{
|
||||
emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2]));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
(define_insn "*xmulxhi_sp64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" "%r"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" "rI"))]
|
||||
UNSPEC_XMUL)
|
||||
(const_int 64))))]
|
||||
"TARGET_VIS3 && TARGET_ARCH64"
|
||||
"xmulxhi\t%1, %2, %0"
|
||||
[(set_attr "type" "imul")])
|
||||
|
||||
(define_insn "xmulxhi_v8plus"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,h")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(unspec:TI [(zero_extend:TI
|
||||
(match_operand:DI 1 "arith_operand" "%r,0"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "arith_operand" "rI,rI"))]
|
||||
UNSPEC_XMUL)
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:SI 3 "=&h,X"))
|
||||
(clobber (match_scratch:SI 4 "=&h,X"))]
|
||||
"TARGET_VIS3 && !TARGET_ARCH64"
|
||||
"* return output_v8plus_mult (insn, operands, \"xmulxhi\");"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length" "9,8")])
|
||||
|
||||
(include "sync.md")
|
||||
|
|
|
|||
|
|
@ -627,4 +627,67 @@ __vis_fucmpeq8 (__v8qi __A, __v8qi __B)
|
|||
return __builtin_vis_fucmpeq8 (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline float
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fhadds (float __A, float __B)
|
||||
{
|
||||
return __builtin_vis_fhadds (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline double
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fhaddd (double __A, double __B)
|
||||
{
|
||||
return __builtin_vis_fhaddd (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline float
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fhsubs (float __A, float __B)
|
||||
{
|
||||
return __builtin_vis_fhsubs (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline double
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fhsubd (double __A, double __B)
|
||||
{
|
||||
return __builtin_vis_fhsubd (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline float
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fnhadds (float __A, float __B)
|
||||
{
|
||||
return __builtin_vis_fnhadds (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline double
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_fnhaddd (double __A, double __B)
|
||||
{
|
||||
return __builtin_vis_fnhaddd (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline __i64
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_umulxhi (__i64 __A, __i64 __B)
|
||||
{
|
||||
return __builtin_vis_umulxhi (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline __i64
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_xmulx (__i64 __A, __i64 __B)
|
||||
{
|
||||
return __builtin_vis_xmulx (__A, __B);
|
||||
}
|
||||
|
||||
extern __inline __i64
|
||||
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
|
||||
__vis_xmulxhi (__i64 __A, __i64 __B)
|
||||
{
|
||||
return __builtin_vis_xmulxhi (__A, __B);
|
||||
}
|
||||
|
||||
#endif /* _VISINTRIN_H_INCLUDED */
|
||||
|
|
|
|||
|
|
@ -13099,6 +13099,17 @@ long __builtin_vis_fucmple8 (v8qi, v8qi);
|
|||
long __builtin_vis_fucmpne8 (v8qi, v8qi);
|
||||
long __builtin_vis_fucmpgt8 (v8qi, v8qi);
|
||||
long __builtin_vis_fucmpeq8 (v8qi, v8qi);
|
||||
|
||||
float __builtin_vis_fhadds (float, float);
|
||||
double __builtin_vis_fhaddd (double, double);
|
||||
float __builtin_vis_fhsubs (float, float);
|
||||
double __builtin_vis_fhsubd (double, double);
|
||||
float __builtin_vis_fnhadds (float, float);
|
||||
double __builtin_vis_fnhaddd (double, double);
|
||||
|
||||
int64_t __builtin_vis_umulxhi (int64_t, int64_t);
|
||||
int64_t __builtin_vis_xmulx (int64_t, int64_t);
|
||||
int64_t __builtin_vis_xmulxhi (int64_t, int64_t);
|
||||
@end smallexample
|
||||
|
||||
@node SPU Built-in Functions
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2011-10-04 David S. Miller <davem@davemloft.net>
|
||||
|
||||
* gcc.target/sparc/fhalve.c: New test.
|
||||
* gcc.target/sparc/fnegop.c: New test.
|
||||
* gcc.target/sparc/xmul.c: New test.
|
||||
|
||||
2011-10-04 Janus Weil <janus@gcc.gnu.org>
|
||||
|
||||
PR fortran/35831
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=niagara3 -mvis" } */
|
||||
|
||||
float test_fhadds (float x, float y)
|
||||
{
|
||||
return __builtin_vis_fhadds (x, y);
|
||||
}
|
||||
|
||||
double test_fhaddd (double x, double y)
|
||||
{
|
||||
return __builtin_vis_fhaddd (x, y);
|
||||
}
|
||||
|
||||
float test_fhsubs (float x, float y)
|
||||
{
|
||||
return __builtin_vis_fhsubs (x, y);
|
||||
}
|
||||
|
||||
double test_fhsubd (double x, double y)
|
||||
{
|
||||
return __builtin_vis_fhsubd (x, y);
|
||||
}
|
||||
|
||||
float test_fnhadds (float x, float y)
|
||||
{
|
||||
return __builtin_vis_fnhadds (x, y);
|
||||
}
|
||||
|
||||
double test_fnhaddd (double x, double y)
|
||||
{
|
||||
return __builtin_vis_fnhaddd (x, y);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fhadds\t%" } } */
|
||||
/* { dg-final { scan-assembler "fhaddd\t%" } } */
|
||||
/* { dg-final { scan-assembler "fhsubs\t%" } } */
|
||||
/* { dg-final { scan-assembler "fhsubd\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnhadds\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnhaddd\t%" } } */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
|
||||
|
||||
float test_fnadds(float x, float y)
|
||||
{
|
||||
return -(x + y);
|
||||
}
|
||||
|
||||
double test_fnaddd(double x, double y)
|
||||
{
|
||||
return -(x + y);
|
||||
}
|
||||
|
||||
float test_fnmuls(float x, float y)
|
||||
{
|
||||
return -(x * y);
|
||||
}
|
||||
|
||||
double test_fnmuld(double x, double y)
|
||||
{
|
||||
return -(x * y);
|
||||
}
|
||||
|
||||
double test_fnsmuld(float x, float y)
|
||||
{
|
||||
return -((double)x * (double)y);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fnadds\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnaddd\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnmuls\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnmuld\t%" } } */
|
||||
/* { dg-final { scan-assembler "fnsmuld\t%" } } */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=niagara3 -mvis" } */
|
||||
typedef long long int64_t;
|
||||
|
||||
int64_t test_umulxhi (int64_t x, int64_t y)
|
||||
{
|
||||
return __builtin_vis_umulxhi (x, y);
|
||||
}
|
||||
|
||||
int64_t test_xmulx (int64_t x, int64_t y)
|
||||
{
|
||||
return __builtin_vis_xmulx (x, y);
|
||||
}
|
||||
|
||||
int64_t test_xmulxhi (int64_t x, int64_t y)
|
||||
{
|
||||
return __builtin_vis_xmulxhi (x, y);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "umulxhi\t%" } } */
|
||||
/* { dg-final { scan-assembler "xmulx\t%" } } */
|
||||
/* { dg-final { scan-assembler "xmulxhi\t%" } } */
|
||||
Loading…
Reference in New Issue