diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 26304ecd795..bf244c018f1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-04-12  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR target/56903
+	* config/i386/i386.c (ix86_hard_regno_mode_ok): Add
+	lra_in_progress for return.
+
 2013-04-12  Greta Yorsh  <Greta.Yorsh@arm.com>
 
 	* config/arm/arm.md (mov_scc,mov_negscc,mov_notscc): Convert
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 9f5a24f6c00..668bddebd6f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -33976,6 +33976,11 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
 	return true;
       if (!TARGET_PARTIAL_REG_STALL)
 	return true;
+      /* LRA checks if the hard register is OK for the given mode.
+        QImode values can live in non-QI regs, so we allow all
+        registers here.  */
+      if (lra_in_progress)
+       return true;
       return !can_create_pseudo_p ();
     }
   /* We handle both integer and floats in the general purpose registers.  */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 29a624e080b..b4fefc5b3f5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-12  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR target/56903
+	* gcc.target/i386/pr56903.c: New test.
+
 2013-04-12  Janus Weil  <janus@gcc.gnu.org>
 
 	PR fortran/56261
diff --git a/gcc/testsuite/gcc.target/i386/pr56903.c b/gcc/testsuite/gcc.target/i386/pr56903.c
new file mode 100644
index 00000000000..9e6a1c3916d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr56903.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/56903 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-additional-options "-march=pentium3" { target ia32 } } */
+
+int a, *b, c;
+struct S { int s : 1; } *fn1 (void);
+extern int fn3 (void), fn4 (int *);
+
+void
+fn2 (void)
+{
+  int e = fn3 ();
+  char f = c + fn1 ()->s * 4;
+  if (*b && f == e)
+    a = *b;
+  fn4 (b);
+}