[AArch64] Fix PR81800

PR81800 is about the lrint inline giving spurious FE_INEXACT exceptions.
The previous change for PR81800 didn't fix this: when lrint is disabled
in the backend, the midend will simply use llrint.  This actually makes
things worse since llrint now also ignores FE_INVALID exceptions!
The fix is to disable lrint/llrint on double if the size of a long is
smaller (ie. ilp32).

    gcc/
	PR target/81800
	* gcc/config/aarch64/aarch64.md (lrint): Disable lrint pattern if GPF
	operand is larger than a long int.

    testsuite/
	PR target/81800
	* gcc.target/aarch64/no-inline-lrint_3.c: New test.

From-SVN: r274376
This commit is contained in:
Wilco Dijkstra 2019-08-13 10:46:44 +00:00 committed by Wilco Dijkstra
parent 4aeb1ba7f6
commit fb802d9146
4 changed files with 29 additions and 1 deletions

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@ -1,3 +1,9 @@
2019-08-13 Wilco Dijkstra <wdijkstr@arm.com>
PR target/81800
* gcc/config/aarch64/aarch64.md (lrint): Disable lrint pattern if GPF
operand is larger than a long int.
2019-08-13 Richard Sandiford <richard.sandiford@arm.com>
* machmode.h (opt_mode::else_mode): New function.

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@ -6323,7 +6323,7 @@
[(match_operand:GPI 0 "register_operand")
(match_operand:GPF 1 "register_operand")]
"TARGET_FLOAT
&& ((GET_MODE_SIZE (<GPF:MODE>mode) <= GET_MODE_SIZE (<GPI:MODE>mode))
&& ((GET_MODE_BITSIZE (<GPF:MODE>mode) <= LONG_TYPE_SIZE)
|| !flag_trapping_math || flag_fp_int_builtin_inexact)"
{
rtx cvt = gen_reg_rtx (<GPF:MODE>mode);

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@ -1,3 +1,8 @@
2019-08-13 Wilco Dijkstra <wdijkstr@arm.com>
PR target/81800
* gcc.target/aarch64/no-inline-lrint_3.c: New test.
2019-08-13 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/init_2.c: Expect ld1rd to be used

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@ -0,0 +1,17 @@
/* { dg-do compile } */
/* { dg-require-effective-target ilp32 } */
/* { dg-options "-O3 -fno-math-errno -fno-fp-int-builtin-inexact" } */
#define TEST(name, float_type, int_type, fn) void f_##name (float_type x) \
{ \
volatile int_type b = __builtin_##fn (x); \
}
TEST (dld, double, long, lrint)
TEST (flf, float , long, lrintf)
TEST (did, double, int, lrint)
TEST (fif, float , int, lrintf)
/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, \[d,s\]\[0-9\]+" 2 } } */
/* { dg-final { scan-assembler-times "bl\tlrint" 2 } } */