From fbaeb717be672acdb109f85765eedc647628d855 Mon Sep 17 00:00:00 2001 From: Kaz Kojima Date: Tue, 3 Jul 2007 16:56:20 +0000 Subject: [PATCH] constraints.md: New file. * config/m32r/constraints.md: New file. * config/m32r/m32r.c: Include tm-constrs.h. (small_data_operand): Use satisfies_constraint_* instead of macro. (addr24_operand, gen_compare): Likewise. * config/m32r/m32r.h (REG_CLASS_FROM_LETTER): Remove. (INT8_P, UPPER16_P, UINT32_P, UINT5_P, INVERTED_SIGNED_8BIT, CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Likewise. * config/m32r/m32r.md: Include constraints.md. (movsi_insn): Use satisfies_constraint_* instead of macro. (andsi3, iorsi3, xorsi3, seq_insn+1, sne): Likewise. * config/m32r/predicates.md (conditional_move_operand): Likewise. (two_insn_const_operand, int8_operand, uint16_operand, reg_or_int16_operand, reg_or_uint16_operand, reg_or_cmp_int16_operand, cmp_int16_operand, seth_add3_operand): Likewise. From-SVN: r126265 --- gcc/ChangeLog | 19 +++++ gcc/config/m32r/constraints.md | 131 +++++++++++++++++++++++++++++++++ gcc/config/m32r/m32r.c | 17 ++--- gcc/config/m32r/m32r.h | 82 +-------------------- gcc/config/m32r/m32r.md | 26 +++---- gcc/config/m32r/predicates.md | 25 +++---- 6 files changed, 184 insertions(+), 116 deletions(-) create mode 100644 gcc/config/m32r/constraints.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 59d4524c976..3915974ed41 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2007-07-01 Kaz Kojima + + * config/m32r/constraints.md: New file. + * config/m32r/m32r.c: Include tm-constrs.h. + (small_data_operand): Use satisfies_constraint_* instead of macro. + (addr24_operand, gen_compare): Likewise. + * config/m32r/m32r.h (REG_CLASS_FROM_LETTER): Remove. + (INT8_P, UPPER16_P, UINT32_P, UINT5_P, INVERTED_SIGNED_8BIT, + CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, + EXTRA_CONSTRAINT): Likewise. + * config/m32r/m32r.md: Include constraints.md. + (*movsi_insn): Use satisfies_constraint_* instead of macro. + (andsi3, iorsi3, xorsi3, seq_insn+1, sne): Likewise. + * config/m32r/predicates.md (conditional_move_operand): Likewise. + (two_insn_const_operand, int8_operand, uint16_operand, + reg_or_int16_operand, reg_or_uint16_operand, + reg_or_cmp_int16_operand, cmp_int16_operand, + seth_add3_operand): Likewise. + 2007-07-03 Eric Christopher * libgcc2.h: Conditionally declare __bswapsi2 and diff --git a/gcc/config/m32r/constraints.md b/gcc/config/m32r/constraints.md new file mode 100644 index 00000000000..c9563fa5ded --- /dev/null +++ b/gcc/config/m32r/constraints.md @@ -0,0 +1,131 @@ +;; Constraint definitions for Renesas M32R cpu for GNU C compiler +;; Copyright (C) 2007 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 2, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, +;; Boston, MA 02110-1301, USA. + + +;; The letters I, J, K, L, M, N, O, P in a register constraint string +;; can be used to stand for particular ranges of immediate operands. +;; The letters Q, R, S, T, U are used to segregate specific types of +;; operands, usually memory references, for the target machine. +;; +;; I is used for 8-bit signed immediates. +;; J is used for 16-bit signed immediates. +;; K is used for 16-bit unsigned immediates. +;; L is used for 16-bit immediates left shifted by 16 (sign ???). +;; M is used for 24-bit unsigned immediates. +;; N is used for 8-bit signed immediates for compares +;; (values in the range -127 to +128). +;; O is used for 5-bit unsigned immediates (shift count). +;; P is used for 16-bit signed immediates for compares +;; (values in the range -32767 to +32768). +;; +;; Q is for symbolic addresses loadable with ld24. +;; R is for symbolic addresses when ld24 can't be used. +;; S is for stores with pre {inc,dec}rement +;; T is for indirect of a pointer. +;; U is for loads with post increment. +;; +;; Register constraints + +(define_register_constraint "a" "ACCUM_REGS" + "@internal") + +(define_register_constraint "c" "CARRY_REG" + "@internal") + +;; Integer constraints +(define_constraint "I" + "8-bit signed immediate." + (and (match_code "const_int") + (match_test "ival >= -0x80 && ival <= 0x7f"))) + +(define_constraint "J" + "16-bit signed immediate." + (and (match_code "const_int") + (match_test "ival >= -0x8000 && ival <= 0x7fff"))) + +(define_constraint "K" + "16-bit unsigned immediate." + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) ival <= 0x0000ffff"))) + +(define_constraint "L" + "16-bit signed immediate left shifted by 16." + (and (match_code "const_int") + (match_test "(ival & 0xffff) == 0") + (match_test "(ival >> 16) >= -0x8000 && (ival >> 16) <= 0x7fff"))) + +(define_constraint "M" + "24-bit unsigned immediate." + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) ival <= 0x00ffffff"))) + +(define_constraint "N" + "8-bit signed immediate for compare." + (and (match_code "const_int") + (match_test "ival >= -127 && ival <= 128"))) + +(define_constraint "O" + "5-bit unsigned immediate." + (and (match_code "const_int") + (match_test "ival >= 0 && ival < 32"))) + +(define_constraint "P" + "16-bit signed immediate for compare." + (and (match_code "const_int") + (match_test "ival >= -0x7fff && ival <= 0x8000"))) + +;; Floating-point constraints +(define_constraint "G" + "Double constant loadable with 2 ldi insns." + (and (match_code "const_double") + (match_test "easy_di_const (op)"))) + +(define_constraint "H" + "Double constant loadable with movdf." + (and (match_code "const_double") + (match_test "easy_df_const (op)"))) + +;; Extra constraints +(define_constraint "Q" + "A symbolic addresse loadable when ld24." + (ior (and (match_test "TARGET_ADDR24") + (match_test "GET_CODE (op) == LABEL_REF")) + (match_test "addr24_operand (op, VOIDmode)"))) + +(define_constraint "R" + "A symbolic addresse loadable with ld24 can't be used." + (ior (and (match_test "TARGET_ADDR32") + (match_test "GET_CODE (op) == LABEL_REF")) + (match_test "addr32_operand (op, VOIDmode)"))) + +(define_constraint "S" + "A store with pre {inc,dec}rement." + (and (match_code "mem") + (match_test "STORE_PREINC_PREDEC_P (GET_MODE (op), XEXP (op, 0))"))) + +(define_constraint "T" + "An indirect of a pointer." + (and (match_code "mem") + (match_test "memreg_operand (op, GET_MODE (op))"))) + +(define_constraint "U" + "A load with post increment." + (and (match_code "mem") + (match_test "LOAD_POSTINC_P (GET_MODE (op), XEXP (op, 0))"))) diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index fa0a6ad9eb0..6758d1a579d 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -42,6 +42,7 @@ #include "tm_p.h" #include "target.h" #include "target-def.h" +#include "tm-constrs.h" /* Save the operands last given to a compare for use when we generate a scc or bcc insn. */ @@ -508,8 +509,7 @@ small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1)))) + && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0)); return 0; @@ -533,8 +533,7 @@ addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) else if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1)))) + && satisfies_constraint_M (XEXP (XEXP (op, 0), 1))) sym = XEXP (XEXP (op, 0), 0); else return 0; @@ -691,8 +690,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) switch (compare_code) { case EQ: - if (GET_CODE (y) == CONST_INT - && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */ + if (satisfies_constraint_P (y) /* Reg equal to small const. */ && y != const0_rtx) { rtx tmp = gen_reg_rtx (SImode); @@ -718,7 +716,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) case LT: if (register_operand (y, SImode) - || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y)))) + || satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */ @@ -758,7 +756,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) case LTU: if (register_operand (y, SImode) - || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y)))) + || satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */ @@ -814,8 +812,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) /* Reg/smallconst equal comparison. */ if (compare_code == EQ - && GET_CODE (y) == CONST_INT - && CMP_INT16_P (INTVAL (y))) + && satisfies_constraint_P (y)) { rtx tmp = gen_reg_rtx (SImode); diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 637ed06ff6e..3b22347d191 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, Renesas M32R cpu. Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, - 2005, 2006 Free Software Foundation, Inc. + 2005, 2006, 2007 Free Software Foundation, Inc. This file is part of GCC. @@ -671,11 +671,6 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS -#define REG_CLASS_FROM_LETTER(C) \ - ( (C) == 'c' ? CARRY_REG \ - : (C) == 'a' ? ACCUM_REGS \ - : NO_REGS) - /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. @@ -699,85 +694,16 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -/* The letters I, J, K, L, M, N, O, P in a register constraint string - can be used to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. */ -/* 'I' is used for 8-bit signed immediates. - 'J' is used for 16-bit signed immediates. - 'K' is used for 16-bit unsigned immediates. - 'L' is used for 16-bit immediates left shifted by 16 (sign ???). - 'M' is used for 24-bit unsigned immediates. - 'N' is used for any 32-bit non-symbolic value. - 'O' is used for 5-bit unsigned immediates (shift count). - 'P' is used for 16-bit signed immediates for compares - (values in the range -32767 to +32768). */ - /* Return true if a value is inside a range. */ -#define IN_RANGE_P(VALUE, LOW, HIGH) \ - (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ +#define IN_RANGE_P(VALUE, LOW, HIGH) \ + (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) -/* Local to this file. */ -#define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f) +/* Some range macros. */ #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) -#define UPPER16_P(X) (((X) & 0xffff) == 0 \ - && ((X) >> 16) >= - 0x8000 \ - && ((X) >> 16) <= 0x7fff) #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) -#define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff) -#define UINT5_P(X) ((X) >= 0 && (X) < 32) -#define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128) - -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ( (C) == 'I' ? INT8_P (VALUE) \ - : (C) == 'J' ? INT16_P (VALUE) \ - : (C) == 'K' ? UINT16_P (VALUE) \ - : (C) == 'L' ? UPPER16_P (VALUE) \ - : (C) == 'M' ? UINT24_P (VALUE) \ - : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \ - : (C) == 'O' ? UINT5_P (VALUE) \ - : (C) == 'P' ? CMP_INT16_P (VALUE) \ - : 0) - -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. - For the m32r, handle a few constants inline. - ??? We needn't treat DI and DF modes differently, but for now we do. */ -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ( (C) == 'G' ? easy_di_const (VALUE) \ - : (C) == 'H' ? easy_df_const (VALUE) \ - : 0) - -/* A C expression that defines the optional machine-dependent constraint - letters that can be used to segregate specific types of operands, - usually memory references, for the target machine. It should return 1 if - VALUE corresponds to the operand type represented by the constraint letter - C. If C is not defined as an extra constraint, the value returned should - be 0 regardless of VALUE. */ -/* Q is for symbolic addresses loadable with ld24. - R is for symbolic addresses when ld24 can't be used. - S is for stores with pre {inc,dec}rement - T is for indirect of a pointer. - U is for loads with post increment. */ - -#define EXTRA_CONSTRAINT(VALUE, C) \ - ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \ - || addr24_operand (VALUE, VOIDmode)) \ - : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \ - || addr32_operand (VALUE, VOIDmode)) \ - : (C) == 'S' ? (GET_CODE (VALUE) == MEM \ - && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \ - XEXP (VALUE, 0))) \ - : (C) == 'T' ? (GET_CODE (VALUE) == MEM \ - && memreg_operand (VALUE, GET_MODE (VALUE))) \ - : (C) == 'U' ? (GET_CODE (VALUE) == MEM \ - && LOAD_POSTINC_P (GET_MODE (VALUE), \ - XEXP (VALUE, 0))) \ - : 0) /* Stack layout and stack pointer usage. */ diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index a4db130ece2..33ef4d94d6d 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -200,6 +200,7 @@ (include "predicates.md") +(include "constraints.md") ;; Expand prologue as RTL (define_expand "prologue" @@ -388,14 +389,13 @@ return \"ld %0,%1\"; case CONST_INT: - value = INTVAL (operands[1]); - if (INT16_P (value)) + if (satisfies_constraint_J (operands[1])) return \"ldi %0,%#%1\\t; %X1\"; - if (UINT24_P (value)) + if (satisfies_constraint_M (operands[1])) return \"ld24 %0,%#%1\\t; %X1\"; - if (UPPER16_P (value)) + if (satisfies_constraint_L (operands[1])) return \"seth %0,%#%T1\\t; %X1\"; return \"#\"; @@ -834,7 +834,7 @@ ; (match_operand:SI 2 "int8_operand" "")))] ; "reload_completed ; && REGNO (operands[0]) != REGNO (operands[1]) -; && INT8_P (INTVAL (operands[2])) +; && satisfies_constraint_I (operands[2]) ; && INTVAL (operands[2]) != 0" ; [(set (match_dup 0) (match_dup 1)) ; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] @@ -1034,8 +1034,7 @@ short instructions, which might eliminate a NOP being inserted. */ if (optimize_size && m32r_not_same_reg (operands[0], operands[1]) - && GET_CODE (operands[2]) == CONST_INT - && INT8_P (INTVAL (operands[2]))) + && satisfies_constraint_I (operands[2])) return \"#\"; else if (GET_CODE (operands[2]) == CONST_INT) @@ -1066,8 +1065,7 @@ short instructions, which might eliminate a NOP being inserted. */ if (optimize_size && m32r_not_same_reg (operands[0], operands[1]) - && GET_CODE (operands[2]) == CONST_INT - && INT8_P (INTVAL (operands[2]))) + && satisfies_constraint_I (operands[2])) return \"#\"; else if (GET_CODE (operands[2]) == CONST_INT) @@ -1098,8 +1096,7 @@ short instructions, which might eliminate a NOP being inserted. */ if (optimize_size && m32r_not_same_reg (operands[0], operands[1]) - && GET_CODE (operands[2]) == CONST_INT - && INT8_P (INTVAL (operands[2]))) + && satisfies_constraint_I (operands[2])) return \"#\"; else if (GET_CODE (operands[2]) == CONST_INT) @@ -1732,8 +1729,7 @@ op1 = op3; } - if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0 - && CMP_INT16_P (value)) + if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0) emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value))); else emit_insn (gen_xorsi3 (op3, op1, op2)); @@ -1757,8 +1753,8 @@ if (mode != SImode) FAIL; - if (GET_CODE (op2) != CONST_INT - || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2)))) + if (GET_CODE (op2) != CONST_INT + || (INTVAL (op2) != 0 && satisfies_constraint_K (op2))) { rtx reg; diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md index 026a3cfc8f3..de161c68f5e 100644 --- a/gcc/config/m32r/predicates.md +++ b/gcc/config/m32r/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas M32R. -;; Copyright (C) 2005 Free Software Foundation, Inc. +;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -51,7 +51,7 @@ return 1; case CONST_INT: - return INT8_P (INTVAL (op)); + return satisfies_constraint_I (op); default: #if 0 @@ -229,9 +229,9 @@ { if (GET_CODE (op) != CONST_INT) return 0; - if (INT16_P (INTVAL (op)) - || UINT24_P (INTVAL (op)) - || UPPER16_P (INTVAL (op))) + if (satisfies_constraint_J (op) + || satisfies_constraint_M (op) + || satisfies_constraint_L (op)) return 0; return 1; }) @@ -260,7 +260,7 @@ { if (GET_CODE (op) != CONST_INT) return 0; - return INT8_P (INTVAL (op)); + return satisfies_constraint_I (op); }) ;; Return true if OP is an unsigned 16-bit immediate value. @@ -270,7 +270,7 @@ { if (GET_CODE (op) != CONST_INT) return 0; - return UINT16_P (INTVAL (op)); + return satisfies_constraint_K (op); }) ;; Return true if OP is a register or signed 16-bit value. @@ -282,7 +282,7 @@ return register_operand (op, mode); if (GET_CODE (op) != CONST_INT) return 0; - return INT16_P (INTVAL (op)); + return satisfies_constraint_J (op); }) ;; Return true if OP is a register or an unsigned 16-bit value. @@ -294,7 +294,7 @@ return register_operand (op, mode); if (GET_CODE (op) != CONST_INT) return 0; - return UINT16_P (INTVAL (op)); + return satisfies_constraint_K (op); }) ;; Return true if OP is a register or signed 16-bit value for @@ -307,7 +307,7 @@ return register_operand (op, mode); if (GET_CODE (op) != CONST_INT) return 0; - return CMP_INT16_P (INTVAL (op)); + return satisfies_constraint_P (op); }) ;; Return true if OP is a register or an integer value that can be @@ -338,7 +338,7 @@ { if (GET_CODE (op) != CONST_INT) return 0; - return CMP_INT16_P (INTVAL (op)); + return satisfies_constraint_P (op); }) ;; Acceptable arguments to the call insn. @@ -434,8 +434,7 @@ if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1)))) + && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) return 1; return 0;