diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e7529f15d39..9b5a67bb52f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2003-02-18  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/mips/mips.h (enum processor_type): Sort entries
+	alphabetically.
+	* config/mips/mips.md (define_attr cpu): Sync with processor_type
+	enum values, including adding entries that were missing.
+
 Tue Feb 18 20:15:54 2003  J"orn Rennecke <joern.rennecke@superh.com>
 
 	* sh.c (calc_live_regs): Also check GET_CODE when checking if initial value
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e76a7395259..d1f02b85a0c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -58,6 +58,10 @@ enum delay_type {
 
 enum processor_type {
   PROCESSOR_DEFAULT,
+  PROCESSOR_4KC,
+  PROCESSOR_5KC,
+  PROCESSOR_20KC,
+  PROCESSOR_M4K,
   PROCESSOR_R3000,
   PROCESSOR_R3900,
   PROCESSOR_R6000,
@@ -72,12 +76,8 @@ enum processor_type {
   PROCESSOR_R5400,
   PROCESSOR_R5500,
   PROCESSOR_R8000,
-  PROCESSOR_4KC,
-  PROCESSOR_5KC,
-  PROCESSOR_20KC,
-  PROCESSOR_M4K,
-  PROCESSOR_SR71000,
-  PROCESSOR_SB1
+  PROCESSOR_SB1,
+  PROCESSOR_SR71000
 };
 
 /* Recast the cpu class to be the cpu attribute.  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 0f67e3f1e82..a477d8799a0 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -125,7 +125,7 @@
 
 ;; ??? Fix everything that tests this attribute.
 (define_attr "cpu"
-  "default,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
+  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sb1,sr71000"
   (const (symbol_ref "mips_cpu_attr")))
 
 ;; Does the instruction have a mandatory delay slot?