i386.c (ix86_osf_output_function_prologue): Remove prototype and function.
2002-06-10 Eric Christopher <echristo@redhat.com> * config/i386/i386.c (ix86_osf_output_function_prologue): Remove prototype and function. (TARGET_ASM_FUNCTION_PROLOGUE): Remove OSF version. (call_insn_operand): Remove half pic references. (legitimate_address_p): Ditto. * config/i386/i386.h: Remove half pic defines. From-SVN: r54451
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@ -1,3 +1,12 @@
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2002-06-10 Eric Christopher <echristo@redhat.com>
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* config/i386/i386.c (ix86_osf_output_function_prologue): Remove
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prototype and function.
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(TARGET_ASM_FUNCTION_PROLOGUE): Remove OSF version.
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(call_insn_operand): Remove half pic references.
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(legitimate_address_p): Ditto.
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* config/i386/i386.h: Remove half pic defines.
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2002-06-10 Eric Christopher <echristo@redhat.com>
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* doc/extend.texi (Return Address): Add note explaining the side-
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@ -49,7 +49,7 @@ Boston, MA 02111-1307, USA. */
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#endif
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/* Processor costs (relative to an add) */
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static const
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static const
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struct processor_costs size_cost = { /* costs for tunning for size */
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2, /* cost of an add instruction */
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3, /* cost of a lea instruction */
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@ -86,7 +86,7 @@ struct processor_costs size_cost = { /* costs for tunning for size */
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0, /* number of parallel prefetches */
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};
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/* Processor costs (relative to an add) */
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static const
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static const
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struct processor_costs i386_cost = { /* 386 specific costs */
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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@ -123,7 +123,7 @@ struct processor_costs i386_cost = { /* 386 specific costs */
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0, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs i486_cost = { /* 486 specific costs */
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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@ -160,7 +160,7 @@ struct processor_costs i486_cost = { /* 486 specific costs */
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0, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs pentium_cost = {
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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@ -197,7 +197,7 @@ struct processor_costs pentium_cost = {
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0, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs pentiumpro_cost = {
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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@ -234,7 +234,7 @@ struct processor_costs pentiumpro_cost = {
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6, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs k6_cost = {
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1, /* cost of an add instruction */
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2, /* cost of a lea instruction */
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@ -271,7 +271,7 @@ struct processor_costs k6_cost = {
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1, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs athlon_cost = {
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1, /* cost of an add instruction */
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2, /* cost of a lea instruction */
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@ -308,7 +308,7 @@ struct processor_costs athlon_cost = {
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6, /* number of parallel prefetches */
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};
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static const
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static const
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struct processor_costs pentium4_cost = {
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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@ -801,12 +801,6 @@ static enum x86_64_reg_class merge_classes PARAMS ((enum x86_64_reg_class,
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#undef TARGET_EXPAND_BUILTIN
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#define TARGET_EXPAND_BUILTIN ix86_expand_builtin
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#if defined (OSF_OS) || defined (TARGET_OSF1ELF)
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static void ix86_osf_output_function_prologue PARAMS ((FILE *,
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HOST_WIDE_INT));
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# undef TARGET_ASM_FUNCTION_PROLOGUE
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# define TARGET_ASM_FUNCTION_PROLOGUE ix86_osf_output_function_prologue
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#endif
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#undef TARGET_ASM_FUNCTION_EPILOGUE
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#define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
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@ -841,7 +835,7 @@ static enum x86_64_reg_class merge_classes PARAMS ((enum x86_64_reg_class,
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#define TARGET_SCHED_INIT ix86_sched_init
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#undef TARGET_SCHED_REORDER
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#define TARGET_SCHED_REORDER ix86_sched_reorder
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#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
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#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
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#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
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ia32_use_dfa_pipeline_interface
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#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
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@ -1040,7 +1034,7 @@ override_options ()
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/* Arrange to set up i386_stack_locals for all functions. */
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init_machine_status = ix86_init_machine_status;
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/* Validate -mregparm= value. */
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if (ix86_regparm_string)
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{
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@ -1208,7 +1202,7 @@ override_options ()
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else
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ix86_fpmath = FPMATH_SSE | FPMATH_387;
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}
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else
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else
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error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
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}
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@ -1354,105 +1348,6 @@ ix86_handle_regparm_attribute (node, name, args, flags, no_add_attrs)
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return NULL_TREE;
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}
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#if defined (OSF_OS) || defined (TARGET_OSF1ELF)
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/* Generate the assembly code for function entry. FILE is a stdio
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stream to output the code to. SIZE is an int: how many units of
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temporary storage to allocate.
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Refer to the array `regs_ever_live' to determine which registers to
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save; `regs_ever_live[I]' is nonzero if register number I is ever
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used in the function. This function is responsible for knowing
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which registers should not be saved even if used.
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We override it here to allow for the new profiling code to go before
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the prologue and the old mcount code to go after the prologue (and
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after %ebx has been set up for ELF shared library support). */
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static void
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ix86_osf_output_function_prologue (file, size)
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FILE *file;
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HOST_WIDE_INT size;
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{
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const char *prefix = "";
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const char *const lprefix = LPREFIX;
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int labelno = current_function_profile_label_no;
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#ifdef OSF_OS
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if (TARGET_UNDERSCORES)
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prefix = "_";
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if (current_function_profile && OSF_PROFILE_BEFORE_PROLOGUE)
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{
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if (!flag_pic && !HALF_PIC_P ())
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{
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fprintf (file, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);
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fprintf (file, "\tcall *%s_mcount_ptr\n", prefix);
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}
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else if (HALF_PIC_P ())
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{
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rtx symref;
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HALF_PIC_EXTERNAL ("_mcount_ptr");
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symref = HALF_PIC_PTR (gen_rtx_SYMBOL_REF (Pmode,
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"_mcount_ptr"));
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fprintf (file, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);
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fprintf (file, "\tmovl %s%s,%%eax\n", prefix,
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XSTR (symref, 0));
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fprintf (file, "\tcall *(%%eax)\n");
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}
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else
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{
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static int call_no = 0;
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fprintf (file, "\tcall %sPc%d\n", lprefix, call_no);
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fprintf (file, "%sPc%d:\tpopl %%eax\n", lprefix, call_no);
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fprintf (file, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n",
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lprefix, call_no++);
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fprintf (file, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",
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lprefix, labelno);
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fprintf (file, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",
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prefix);
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fprintf (file, "\tcall *(%%eax)\n");
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}
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}
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#else /* !OSF_OS */
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if (current_function_profile && OSF_PROFILE_BEFORE_PROLOGUE)
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{
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if (!flag_pic)
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{
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fprintf (file, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);
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fprintf (file, "\tcall *%s_mcount_ptr\n", prefix);
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}
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else
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{
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static int call_no = 0;
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fprintf (file, "\tcall %sPc%d\n", lprefix, call_no);
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fprintf (file, "%sPc%d:\tpopl %%eax\n", lprefix, call_no);
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fprintf (file, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n",
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lprefix, call_no++);
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fprintf (file, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",
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lprefix, labelno);
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fprintf (file, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",
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prefix);
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fprintf (file, "\tcall *(%%eax)\n");
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}
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}
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#endif /* !OSF_OS */
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function_prologue (file, size);
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}
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#endif /* OSF_OS || TARGET_OSF1ELF */
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/* Return 0 if the attributes for two types are incompatible, 1 if they
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are compatible, and 2 if they are nearly compatible (which causes a
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warning to be generated). */
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@ -2403,9 +2298,9 @@ ix86_build_va_list ()
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record = (*lang_hooks.types.make_type) (RECORD_TYPE);
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type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
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f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
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f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
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unsigned_type_node);
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f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
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f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
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unsigned_type_node);
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f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
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ptr_type_node);
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}
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/* Perform any needed actions needed for a function that is receiving a
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variable number of arguments.
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variable number of arguments.
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CUM is as above.
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@ -2999,7 +2894,7 @@ pic_symbolic_operand (op, mode)
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if (GET_CODE (XEXP (op, 0)) == UNSPEC)
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return 1;
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}
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else
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else
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{
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if (GET_CODE (op) == UNSPEC)
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return 1;
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@ -3037,7 +2932,7 @@ local_symbolic_operand (op, mode)
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return 1;
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/* There is, however, a not insubstantial body of code in the rest of
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the compiler that assumes it can just stick the results of
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the compiler that assumes it can just stick the results of
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ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
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/* ??? This is a hack. Should update the body of the compiler to
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always create a DECL an invoke targetm.encode_section_info. */
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if (GET_CODE (op) == SYMBOL_REF)
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return 1;
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/* Half-pic doesn't allow anything but registers and constants.
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We've just taken care of the later. */
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if (HALF_PIC_P ())
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return register_operand (op, Pmode);
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/* Otherwise we can allow any general_operand in the address. */
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return general_operand (op, Pmode);
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}
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return INVALID_REGNUM;
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}
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/* Return 1 if we need to save REGNO. */
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static int
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ix86_save_reg (regno, maybe_eh_return)
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@ -4965,7 +4855,7 @@ constant_address_p (x)
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}
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/* Nonzero if the constant value X is a legitimate general operand
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when generating PIC code. It is given that flag_pic is on and
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when generating PIC code. It is given that flag_pic is on and
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that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
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bool
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@ -5080,7 +4970,7 @@ legitimate_pic_address_disp_p (disp)
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return false;
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return local_dynamic_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
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}
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return 0;
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}
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@ -5291,15 +5181,6 @@ legitimate_address_p (mode, addr, strict)
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that never results in lea, this seems to be easier and
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correct fix for crash to disable this test. */
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}
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else if (HALF_PIC_P ())
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{
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if (! HALF_PIC_ADDRESS_P (disp)
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|| (base != NULL_RTX || index != NULL_RTX))
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{
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reason = "displacement is an invalid half-pic reference";
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goto report_error;
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}
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}
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else if (!CONSTANT_ADDRESS_P (disp))
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{
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reason = "displacement is not constant";
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@ -5582,7 +5463,7 @@ get_thread_pointer ()
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return tp;
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}
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/* Try machine-dependent ways of modifying an illegitimate address
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to be legitimate. If we find one, return the new, valid address.
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This macro is used in only one place: `memory_address' in explow.c.
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@ -6528,7 +6409,7 @@ print_operand (file, x, code)
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/* Like above, but reverse condition */
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case 'c':
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/* Check to see if argument to %c is really a constant
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/* Check to see if argument to %c is really a constant
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and not a condition code which needs to be reversed. */
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if (GET_RTX_CLASS (GET_CODE (x)) != '<')
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{
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@ -7565,7 +7446,7 @@ ix86_expand_vector_move (mode, operands)
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}
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
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}
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}
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/* Attempt to expand a binary operator. Make the expansion closer to the
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actual machine, then just general_operand, which will allow 3 separate
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@ -8430,7 +8311,7 @@ ix86_expand_branch (code, label)
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code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
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&ix86_compare_op1);
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ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
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/* Check whether we will use the natural sequence with one jump. If
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@ -10626,7 +10507,7 @@ ix86_expand_call (retval, fnaddr, callarg1, callarg2, pop)
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if (use)
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CALL_INSN_FUNCTION_USAGE (call) = use;
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}
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/* Clear stack slot assignments remembered from previous functions.
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This is called from INIT_EXPANDERS once before RTL is emitted for each
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@ -11214,7 +11095,7 @@ ix86_sched_reorder (dump, sched_verbose, ready, n_readyp, clock_var)
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int n_ready = *n_readyp;
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rtx *e_ready = ready + n_ready - 1;
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/* Make sure to go ahead and initialize key items in
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/* Make sure to go ahead and initialize key items in
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ix86_sched_data if we are not going to bother trying to
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reorder the ready queue. */
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if (n_ready < 2)
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@ -12689,7 +12570,7 @@ ix86_expand_binop_builtin (icode, arglist, target)
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return target;
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}
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/* In type_for_mode we restrict the ability to create TImode types
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/* In type_for_mode we restrict the ability to create TImode types
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to hosts with 64-bit H_W_I. So we've defined the SSE logicals
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to have a V4SFmode signature. Convert them in-place to TImode. */
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|
@ -12819,11 +12700,11 @@ ix86_expand_unop1_builtin (icode, arglist, target)
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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op1 = op0;
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
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op1 = copy_to_mode_reg (mode0, op1);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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return 0;
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@ -13820,7 +13701,7 @@ x86_order_regs_for_local_alloc ()
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if (!TARGET_SSE_MATH)
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for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
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reg_alloc_order [pos++] = i;
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/* SSE registers. */
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for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
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reg_alloc_order [pos++] = i;
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|
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@ -34,20 +34,6 @@ Boston, MA 02111-1307, USA. */
|
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ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
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that start with ASM_ or end in ASM_OP. */
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/* Stubs for half-pic support if not OSF/1 reference platform. */
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#ifndef HALF_PIC_P
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#define HALF_PIC_P() 0
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#define HALF_PIC_NUMBER_PTRS 0
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#define HALF_PIC_NUMBER_REFS 0
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#define HALF_PIC_ENCODE(DECL)
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#define HALF_PIC_DECLARE(NAME)
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#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
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||||
#define HALF_PIC_ADDRESS_P(X) 0
|
||||
#define HALF_PIC_PTR(X) (X)
|
||||
#define HALF_PIC_FINISH(STREAM)
|
||||
#endif
|
||||
|
||||
/* Define the specific costs for a given cpu */
|
||||
|
||||
struct processor_costs {
|
||||
|
@ -140,7 +126,7 @@ extern int target_flags;
|
|||
|
||||
/* Compile using ret insn that pops args.
|
||||
This will not work unless you use prototypes at least
|
||||
for all functions that can take varying numbers of args. */
|
||||
for all functions that can take varying numbers of args. */
|
||||
#define TARGET_RTD (target_flags & MASK_RTD)
|
||||
|
||||
/* Align doubles to a two word boundary. This breaks compatibility with
|
||||
|
@ -712,7 +698,7 @@ extern int x86_prefetch_sse;
|
|||
and all fundamental data types supported by the hardware
|
||||
might need to be aligned. No data type wants to be aligned
|
||||
rounder than this.
|
||||
|
||||
|
||||
Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
|
||||
and Pentium Pro XFmode values at 128 bit boundaries. */
|
||||
|
||||
|
@ -826,7 +812,7 @@ extern int x86_prefetch_sse;
|
|||
/* 1 for registers that have pervasive standard uses
|
||||
and are not available for the register allocator.
|
||||
On the 80386, the stack pointer is such, as is the arg pointer.
|
||||
|
||||
|
||||
The value is an mask - bit 1 is set for fixed registers
|
||||
for 32bit target, while 2 is set for fixed registers for 64bit.
|
||||
Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
|
||||
|
@ -844,15 +830,15 @@ extern int x86_prefetch_sse;
|
|||
1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
|
||||
1, 1, 1, 1, 1, 1, 1, 1}
|
||||
|
||||
|
||||
|
||||
/* 1 for registers not available across function calls.
|
||||
These must include the FIXED_REGISTERS and also any
|
||||
registers that can be used without being saved.
|
||||
The latter must include the registers where values are returned
|
||||
and the register where structure-value addresses are passed.
|
||||
Aside from that, you can include as many other registers as you like.
|
||||
|
||||
Aside from that, you can include as many other registers as you like.
|
||||
|
||||
The value is an mask - bit 1 is set for call used
|
||||
for 32bit target, while 2 is set for call used for 64bit.
|
||||
Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
|
||||
|
@ -938,7 +924,7 @@ do { \
|
|||
This is ordinarily the length in words of a value of mode MODE
|
||||
but can be less for certain modes in special long registers.
|
||||
|
||||
Actually there are no two word move instructions for consecutive
|
||||
Actually there are no two word move instructions for consecutive
|
||||
registers. And only registers 0-3 may have mov byte instructions
|
||||
applied to them.
|
||||
*/
|
||||
|
@ -1051,7 +1037,7 @@ do { \
|
|||
|
||||
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
|
||||
#define LAST_SSE_REG (FIRST_SSE_REG + 7)
|
||||
|
||||
|
||||
#define FIRST_MMX_REG (LAST_SSE_REG + 1)
|
||||
#define LAST_MMX_REG (FIRST_MMX_REG + 7)
|
||||
|
||||
|
@ -1087,7 +1073,7 @@ do { \
|
|||
/* Register to hold the addressing base for position independent
|
||||
code access to data items. We don't use PIC pointer for 64bit
|
||||
mode. Define the regnum to dummy value to prevent gcc from
|
||||
pessimizing code dealing with EBX.
|
||||
pessimizing code dealing with EBX.
|
||||
|
||||
To avoid clobbering a call-saved register unnecessarily, we renumber
|
||||
the pic register when possible. The change is visible after the
|
||||
|
@ -1300,7 +1286,7 @@ enum reg_class
|
|||
|
||||
#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
|
||||
#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
|
||||
|
||||
|
||||
#define STACK_REG_P(XOP) \
|
||||
(REG_P (XOP) && \
|
||||
REGNO (XOP) >= FIRST_STACK_REG && \
|
||||
|
@ -1431,7 +1417,7 @@ enum reg_class
|
|||
ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
|
||||
|
||||
/* QImode spills from non-QI registers need a scratch. This does not
|
||||
happen often -- the only example so far requires an uninitialized
|
||||
happen often -- the only example so far requires an uninitialized
|
||||
pseudo. */
|
||||
|
||||
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
|
||||
|
@ -1478,7 +1464,7 @@ enum reg_class
|
|||
|| ((CLASS) == DIREG))
|
||||
|
||||
/* A C statement that adds to CLOBBERS any hard regs the port wishes
|
||||
to automatically clobber for all asms.
|
||||
to automatically clobber for all asms.
|
||||
|
||||
We do this in the new i386 backend to maintain source compatibility
|
||||
with the old cc0-based compiler. */
|
||||
|
@ -1516,7 +1502,7 @@ enum reg_class
|
|||
On 386 pushw decrements by exactly 2 no matter what the position was.
|
||||
On the 386 there is no pushb; we use pushw instead, and this
|
||||
has the effect of rounding up to 2.
|
||||
|
||||
|
||||
For 64bit ABI we round up to 8 bytes.
|
||||
*/
|
||||
|
||||
|
@ -1737,7 +1723,7 @@ do { \
|
|||
the stack pointer does not matter. The value is tested only in
|
||||
functions that have frame pointers.
|
||||
No definition is equivalent to always zero. */
|
||||
/* Note on the 386 it might be more efficient not to define this since
|
||||
/* Note on the 386 it might be more efficient not to define this since
|
||||
we have to restore it ourselves from the frame pointer, in order to
|
||||
use pop */
|
||||
|
||||
|
@ -1956,7 +1942,7 @@ do { \
|
|||
#define REWRITE_ADDRESS(X) rewrite_address (X)
|
||||
|
||||
/* Nonzero if the constant value X is a legitimate general operand
|
||||
when generating PIC code. It is given that flag_pic is on and
|
||||
when generating PIC code. It is given that flag_pic is on and
|
||||
that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
|
||||
|
||||
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
|
||||
|
@ -2146,7 +2132,7 @@ enum ix86_builtins
|
|||
IX86_BUILTIN_RSQRTSS,
|
||||
IX86_BUILTIN_SQRTPS,
|
||||
IX86_BUILTIN_SQRTSS,
|
||||
|
||||
|
||||
IX86_BUILTIN_UNPCKHPS,
|
||||
IX86_BUILTIN_UNPCKLPS,
|
||||
|
||||
|
@ -2519,7 +2505,7 @@ do { \
|
|||
precise value of the constant, which is available for examination
|
||||
in X, and the rtx code of the expression in which it is contained,
|
||||
found in OUTER_CODE.
|
||||
|
||||
|
||||
CODE is the expression code--redundant, since it can be obtained
|
||||
with `GET_CODE (X)'. */
|
||||
|
||||
|
@ -2851,8 +2837,8 @@ do { \
|
|||
/* Add any extra modes needed to represent the condition code.
|
||||
|
||||
For the i386, we need separate modes when floating-point
|
||||
equality comparisons are being done.
|
||||
|
||||
equality comparisons are being done.
|
||||
|
||||
Add CCNO to indicate comparisons against zero that requires
|
||||
Overflow flag to be unset. Sign bit test is used instead and
|
||||
thus can be used to form "a&b>0" type of tests.
|
||||
|
@ -2911,7 +2897,7 @@ do { \
|
|||
For float regs, the stack top is sometimes referred to as "%st(0)"
|
||||
instead of just "%st". PRINT_REG handles this with the "y" code. */
|
||||
|
||||
#undef HI_REGISTER_NAMES
|
||||
#undef HI_REGISTER_NAMES
|
||||
#define HI_REGISTER_NAMES \
|
||||
{"ax","dx","cx","bx","si","di","bp","sp", \
|
||||
"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
|
||||
|
@ -2961,7 +2947,7 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
|
|||
/* Before the prologue, RA is at 0(%esp). */
|
||||
#define INCOMING_RETURN_ADDR_RTX \
|
||||
gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
|
||||
|
||||
|
||||
/* After the prologue, RA is at -4(AP) in the current frame. */
|
||||
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
||||
((COUNT) == 0 \
|
||||
|
@ -3034,7 +3020,7 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
|
|||
#define JUMP_TABLES_IN_TEXT_SECTION \
|
||||
(!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
|
||||
|
||||
/* A C statement that outputs an address constant appropriate to
|
||||
/* A C statement that outputs an address constant appropriate to
|
||||
for DWARF debugging. */
|
||||
|
||||
#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
|
||||
|
@ -3291,7 +3277,7 @@ extern const char *ix86_asm_string;
|
|||
extern enum asm_dialect ix86_asm_dialect;
|
||||
|
||||
extern int ix86_regparm;
|
||||
extern const char *ix86_regparm_string;
|
||||
extern const char *ix86_regparm_string;
|
||||
|
||||
extern int ix86_preferred_stack_boundary;
|
||||
extern const char *ix86_preferred_stack_boundary_string;
|
||||
|
@ -3319,12 +3305,12 @@ extern rtx ix86_compare_op1; /* operand 1 for comparisons */
|
|||
redundant computation of new control word by the mode switching pass.
|
||||
The fldcw instructions are still emitted redundantly, but this is probably
|
||||
not going to be noticeable problem, as most CPUs do have fast path for
|
||||
the sequence.
|
||||
the sequence.
|
||||
|
||||
The machinery is to emit simple truncation instructions and split them
|
||||
before reload to instructions having USEs of two memory locations that
|
||||
are filled by this code to old and new control word.
|
||||
|
||||
|
||||
Post-reload pass may be later used to eliminate the redundant fildcw if
|
||||
needed. */
|
||||
|
||||
|
|
Loading…
Reference in New Issue