* reorg.c: Remove comments about dead ports.
From-SVN: r78280
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@ -1,3 +1,7 @@
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2004-02-22 Kazu Hirata <kazu@cs.umass.edu>
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* reorg.c: Remove comments about dead ports.
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2004-02-22 Christopher Faylor <cgf@redhat.com>
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* config.gcc (i[34567]86-*-pe|i[34567]86-*-cygwin*): *Really* specify
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13
gcc/reorg.c
13
gcc/reorg.c
@ -36,19 +36,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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cycle, and the Branch Penalty is 0. Several RISC machines approach
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branch delays differently:
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The MIPS and AMD 29000 have a single branch delay slot. Most insns
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The MIPS has a single branch delay slot. Most insns
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(except other branches) can be used to fill this slot. When the
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slot is filled, two insns execute in two cycles, reducing the
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branch penalty to zero.
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The Motorola 88000 conditionally exposes its branch delay slot,
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so code is shorter when it is turned off, but will run faster
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when useful insns are scheduled there.
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The IBM ROMP has two forms of branch and call insns, both with and
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without a delay slot. Much like the 88k, insns not using the delay
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slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
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The SPARC always has a branch delay slot, but its effects can be
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annulled when the branch is not taken. This means that failing to
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find other sources of insns, we can hoist an insn from the branch
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@ -84,8 +76,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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`fill_eager_delay_slots' tries to guess the direction the branch
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will go; if it guesses right 100% of the time, it can reduce the
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branch penalty as much as `fill_simple_delay_slots' does. If it
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guesses wrong 100% of the time, it might as well schedule nops (or
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on the m88k, unexpose the branch slot). When
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guesses wrong 100% of the time, it might as well schedule nops. When
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`fill_eager_delay_slots' takes insns from the fall-through path of
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the jump, usually there is no code expansion; when it takes insns
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from the branch target, there is code expansion if it is not the
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