aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter.
gcc/ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter. (aarch64_simd_mov<mode>): New expander. (aarch64_simd_mov_to_<mode>low): New instruction pattern. (aarch64_simd_mov_to_<mode>high): Likewise. (aarch64_simd_mov_from_<mode>low): Likewise. (aarch64_simd_mov_from_<mode>high): Likewise. (aarch64_dup_lane<mode>): Update. (aarch64_dup_lanedi): New instruction pattern. * config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype. * config/aarch64/aarch64.c (aarch64_split_simd_move): New function. testsuites/ * gcc.target/aarch64/scalar_intrinsics.c: Update. From-SVN: r198680
This commit is contained in:
Sofiane Naci
Sofiane Naci
parent
a7a7d10ed5
commit
fd4842cd67
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@ -1,3 +1,16 @@
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2013-05-07 Sofiane Naci <sofiane.naci@arm.com>
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* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter.
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(aarch64_simd_mov<mode>): New expander.
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(aarch64_simd_mov_to_<mode>low): New instruction pattern.
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(aarch64_simd_mov_to_<mode>high): Likewise.
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(aarch64_simd_mov_from_<mode>low): Likewise.
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(aarch64_simd_mov_from_<mode>high): Likewise.
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(aarch64_dup_lane<mode>): Update.
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(aarch64_dup_lanedi): New instruction pattern.
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* config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype.
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* config/aarch64/aarch64.c (aarch64_split_simd_move): New function.
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2013-05-07 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* gimple-ssa-strength-reduction.c (lazy_create_slsr_reg): Remove.
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@ -219,6 +219,8 @@ void aarch64_split_128bit_move (rtx, rtx);
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bool aarch64_split_128bit_move_p (rtx, rtx);
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void aarch64_split_simd_move (rtx, rtx);
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/* Check for a legitimate floating point constant for FMOV. */
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bool aarch64_float_const_representable_p (rtx);
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@ -358,7 +358,7 @@
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)
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(define_insn "aarch64_dup_lane<mode>"
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[(set (match_operand:SDQ_I 0 "register_operand" "=w")
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[(set (match_operand:ALLX 0 "register_operand" "=w")
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(vec_select:<VEL>
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(match_operand:<VCON> 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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@ -369,6 +369,19 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_dup_lanedi"
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[(set (match_operand:DI 0 "register_operand" "=w,r")
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(vec_select:DI
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(match_operand:V2DI 1 "register_operand" "w,w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))]
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"TARGET_SIMD"
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"@
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dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]
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umov\t%0, %1.d[%2]"
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[(set_attr "simd_type" "simd_dup")
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(set_attr "simd_mode" "DI")]
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)
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(define_insn "aarch64_simd_dup<mode>"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))]
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@ -419,8 +432,8 @@
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case 0: return "ld1\t{%0.<Vtype>}, %1";
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case 1: return "st1\t{%1.<Vtype>}, %0";
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case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
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case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]";
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case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1";
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case 3: return "#";
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case 4: return "#";
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case 5: return "#";
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case 6:
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return aarch64_output_simd_mov_immediate (&operands[1],
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@ -454,6 +467,105 @@
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aarch64_simd_disambiguate_copy (operands, dest, src, 2);
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})
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(define_split
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[(set (match_operand:VQ 0 "register_operand" "")
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(match_operand:VQ 1 "register_operand" ""))]
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"TARGET_SIMD && reload_completed
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&& ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1])))
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|| (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))"
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[(const_int 0)]
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{
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aarch64_split_simd_move (operands[0], operands[1]);
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DONE;
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})
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(define_expand "aarch64_simd_mov<mode>"
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[(set (match_operand:VQ 0)
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(match_operand:VQ 1))]
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"TARGET_SIMD"
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{
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rtx dst = operands[0];
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rtx src = operands[1];
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if (GP_REGNUM_P (REGNO (src)))
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{
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rtx low_part = gen_lowpart (<VHALF>mode, src);
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rtx high_part = gen_highpart (<VHALF>mode, src);
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emit_insn
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(gen_aarch64_simd_mov_to_<mode>low (dst, low_part));
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emit_insn
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(gen_aarch64_simd_mov_to_<mode>high (dst, high_part));
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}
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else
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{
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rtx low_half = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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rtx high_half = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
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rtx low_part = gen_lowpart (<VHALF>mode, dst);
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rtx high_part = gen_highpart (<VHALF>mode, dst);
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emit_insn
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(gen_aarch64_simd_mov_from_<mode>low (low_part, src, low_half));
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emit_insn
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(gen_aarch64_simd_mov_from_<mode>high (high_part, src, high_half));
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}
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DONE;
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}
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)
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(define_insn "aarch64_simd_mov_to_<mode>low"
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[(set (zero_extract:VQ
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(match_operand:VQ 0 "register_operand" "+w")
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(const_int 64) (const_int 0))
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(vec_concat:VQ
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(match_operand:<VHALF> 1 "register_operand" "r")
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(vec_duplicate:<VHALF> (const_int 0))))]
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"TARGET_SIMD && reload_completed"
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"ins\t%0.d[0], %1"
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[(set_attr "simd_type" "simd_move")
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(set_attr "simd_mode" "<MODE>")
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(set_attr "length" "4")
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])
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(define_insn "aarch64_simd_mov_to_<mode>high"
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[(set (zero_extract:VQ
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(match_operand:VQ 0 "register_operand" "+w")
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(const_int 64) (const_int 64))
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(vec_concat:VQ
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(match_operand:<VHALF> 1 "register_operand" "r")
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(vec_duplicate:<VHALF> (const_int 0))))]
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"TARGET_SIMD && reload_completed"
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"ins\t%0.d[1], %1"
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[(set_attr "simd_type" "simd_move")
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(set_attr "simd_mode" "<MODE>")
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(set_attr "length" "4")
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])
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(define_insn "aarch64_simd_mov_from_<mode>low"
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[(set (match_operand:<VHALF> 0 "register_operand" "=r")
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(vec_select:<VHALF>
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(match_operand:VQ 1 "register_operand" "w")
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(match_operand:VQ 2 "vect_par_cnst_lo_half" "")))]
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"TARGET_SIMD && reload_completed"
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"umov\t%0, %1.d[0]"
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[(set_attr "simd_type" "simd_move")
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(set_attr "simd_mode" "<MODE>")
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(set_attr "length" "4")
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])
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(define_insn "aarch64_simd_mov_from_<mode>high"
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[(set (match_operand:<VHALF> 0 "register_operand" "=r")
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(vec_select:<VHALF>
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(match_operand:VQ 1 "register_operand" "w")
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(match_operand:VQ 2 "vect_par_cnst_hi_half" "")))]
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"TARGET_SIMD && reload_completed"
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"umov\t%0, %1.d[1]"
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[(set_attr "simd_type" "simd_move")
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(set_attr "simd_mode" "<MODE>")
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(set_attr "length" "4")
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])
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(define_insn "orn<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))
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@ -656,6 +656,47 @@ aarch64_split_128bit_move_p (rtx dst, rtx src)
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|| ! (FP_REGNUM_P (REGNO (dst)) && FP_REGNUM_P (REGNO (src))));
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}
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/* Split a complex SIMD move. */
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void
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aarch64_split_simd_move (rtx dst, rtx src)
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{
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enum machine_mode src_mode = GET_MODE (src);
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enum machine_mode dst_mode = GET_MODE (dst);
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gcc_assert (VECTOR_MODE_P (dst_mode));
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if (REG_P (dst) && REG_P (src))
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{
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gcc_assert (VECTOR_MODE_P (src_mode));
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switch (src_mode)
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{
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case V16QImode:
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emit_insn (gen_aarch64_simd_movv16qi (dst, src));
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break;
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case V8HImode:
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emit_insn (gen_aarch64_simd_movv8hi (dst, src));
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break;
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case V4SImode:
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emit_insn (gen_aarch64_simd_movv4si (dst, src));
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break;
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case V2DImode:
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emit_insn (gen_aarch64_simd_movv2di (dst, src));
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break;
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case V4SFmode:
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emit_insn (gen_aarch64_simd_movv4sf (dst, src));
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break;
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case V2DFmode:
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emit_insn (gen_aarch64_simd_movv2df (dst, src));
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break;
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default:
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gcc_unreachable ();
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}
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return;
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}
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}
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static rtx
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aarch64_force_temporary (rtx x, rtx value)
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{
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@ -1,3 +1,7 @@
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2013-05-07 Sofiane Naci <sofiane.naci@arm.com>
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* gcc.target/aarch64/scalar_intrinsics.c: Update.
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2013-05-07 Richard Biener <rguenther@suse.de>
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PR middle-end/57190
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@ -223,7 +223,7 @@ test_vdups_lane_u32 (uint32x4_t a)
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return vdups_lane_u32 (a, 2);
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}
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/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */
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/* { dg-final { scan-assembler-times "\\tumov\\tx\[0-9\]+, v\[0-9\]+\.d" 2 } } */
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int64x1_t
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test_vdupd_lane_s64 (int64x2_t a)
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