OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV

Browse Source 
There is no need to set mode attribute to XImode nor V8DFmode since
ix86_output_ssemov can properly encode xmm16-xmm31 registers with and
without AVX512VL.

gcc/

	PR target/89229
	* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
	* config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
	TARGET_AVX512VL and ext_sse_reg_operand check.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-4a.c: New test.
	* gcc.target/i386/pr89229-4b.c: Likewise.
	* gcc.target/i386/pr89229-4c.c: Likewise.
This commit is contained in:
H.J. Lu 2020-03-13 02:48:59 -07:00
parent dbf3dc7588
commit fd8679974b
7 changed files with 53 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
PR target/89229
* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
* config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
TARGET_AVX512VL and ext_sse_reg_operand check.
2020-03-13 Bu Le <bule1@huawei.com>
PR target/94154

6
gcc/config/i386/i386.c
View File

@ -5127,6 +5127,12 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands)
else
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
return "vmovsd\t{%d1, %0|%0, %d1}";
else
return "%vmovsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
gcc_assert (!TARGET_AVX);
return "movlpd\t{%1, %0|%0, %1}";

44
gcc/config/i386/i386.md
View File

@ -3355,37 +3355,7 @@
return standard_sse_constant_opcode (insn, operands);
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_DF:
if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
return "vmovsd\t{%d1, %0|%0, %d1}";
return "%vmovsd\t{%1, %0|%0, %1}";
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V8DF:
return "vmovapd\t{%g1, %g0|%g0, %g1}";
case MODE_V2DF:
return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_V2SF:
gcc_assert (!TARGET_AVX);
return "movlps\t{%1, %0|%0, %1}";
case MODE_V1DF:
gcc_assert (!TARGET_AVX);
return "movlpd\t{%1, %0|%0, %1}";
case MODE_DI:
/* Handle broken assemblers that require movd instead of movq. */
if (!HAVE_AS_IX86_INTERUNIT_MOVQ
&& (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
return ix86_output_ssemov (insn, operands);
default:
gcc_unreachable ();
@ -3439,10 +3409,7 @@
/* xorps is one byte shorter for non-AVX targets. */
(eq_attr "alternative" "12,16")
(cond [(and (match_test "TARGET_AVX512F")
(not (match_test "TARGET_PREFER_AVX256")))
(const_string "XI")
(match_test "TARGET_AVX")
(cond [(match_test "TARGET_AVX")
(const_string "V2DF")
(ior (not (match_test "TARGET_SSE2"))
(match_test "optimize_function_for_size_p (cfun)"))
@ -3458,12 +3425,7 @@
/* movaps is one byte shorter for non-AVX targets. */
(eq_attr "alternative" "13,17")
(cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
(not (match_test "TARGET_AVX512VL")))
(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand")))
(const_string "V8DF")
(match_test "TARGET_AVX")
(cond [(match_test "TARGET_AVX")
(const_string "DF")
(ior (not (match_test "TARGET_SSE2"))
(match_test "optimize_function_for_size_p (cfun)"))

7
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
PR target/89229
* gcc.target/i386/pr89229-4a.c: New test.
* gcc.target/i386/pr89229-4b.c: Likewise.
* gcc.target/i386/pr89229-4c.c: Likewise.
2019-03-13 Eric Botcazou <ebotcazou@adacore.com>
* gcc.c-torture/compile/20200313-1.c: New test.

16
gcc/testsuite/gcc.target/i386/pr89229-4a.c Normal file
View File

@ -0,0 +1,16 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512" } */
extern double d;
void
foo1 (double x)
{
register double xmm16 __asm ("xmm16") = x;
asm volatile ("" : "+v" (xmm16));
register double xmm17 __asm ("xmm17") = xmm16;
asm volatile ("" : "+v" (xmm17));
d = xmm17;
}
/* { dg-final { scan-assembler-not "vmovapd" } } */

7
gcc/testsuite/gcc.target/i386/pr89229-4b.c Normal file
View File

@ -0,0 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
#include "pr89229-4a.c"
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
/* { dg-final { scan-assembler-not "vmovapd" } } */

6
gcc/testsuite/gcc.target/i386/pr89229-4c.c Normal file
View File

@ -0,0 +1,6 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
#include "pr89229-4a.c"
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */