power8.md: New.
* config/rs6000/power8.md: New. * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor setting for power8 entry. * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md. * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust test for Power4/Power5 only. (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8 support. (force_new_group): Adjust comment. * config/rs6000/rs6000.md: Include power8.md. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r200423
This commit is contained in:
parent
b24a2ce5b2
commit
fd8c65e7d3
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@ -1,3 +1,18 @@
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2013-06-26 Michael Meissner <meissner@linux.vnet.ibm.com>
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Pat Haugen <pthaugen@us.ibm.com>
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Peter Bergner <bergner@vnet.ibm.com>
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* config/rs6000/power8.md: New.
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* config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor
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setting for power8 entry.
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* config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md.
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* config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust
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test for Power4/Power5 only.
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(insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8
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support.
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(force_new_group): Adjust comment.
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* config/rs6000/rs6000.md: Include power8.md.
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2013-06-26 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/arm.h (MAX_CONDITIONAL_EXECUTE): Define macro.
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@ -0,0 +1,373 @@
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;; Scheduling description for IBM POWER8 processor.
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;; Copyright (C) 2013 Free Software Foundation, Inc.
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;;
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;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
|
||||
;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
;; License for more details.
|
||||
;;
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||||
;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "power8fxu,power8lsu,power8vsu,power8misc")
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(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")
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(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")
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(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")
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(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")
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(define_cpu_unit "bpu_power8,cru_power8" "power8misc")
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(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\
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du5_power8,du6_power8" "power8misc")
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; Dispatch group reservations
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(define_reservation "DU_any_power8"
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"du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\
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du5_power8")
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; 2-way Cracked instructions go in slots 0-1
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; (can also have a second in slots 3-4 if insns are adjacent)
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(define_reservation "DU_cracked_power8"
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"du0_power8+du1_power8")
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; Insns that are first in group
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(define_reservation "DU_first_power8"
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"du0_power8")
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; Insns that are first and last in group
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(define_reservation "DU_both_power8"
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"du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\
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du5_power8+du6_power8")
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; Dispatch slots are allocated in order conforming to program order.
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(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\
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du5_power8,du6_power8")
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(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\
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du6_power8")
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(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")
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(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")
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(absence_set "du4_power8" "du5_power8,du6_power8")
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(absence_set "du5_power8" "du6_power8")
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; Execution unit reservations
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(define_reservation "FXU_power8"
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"fxu0_power8|fxu1_power8")
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(define_reservation "LU_power8"
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"lu0_power8|lu1_power8")
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(define_reservation "LSU_power8"
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"lsu0_power8|lsu1_power8")
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(define_reservation "LU_or_LSU_power8"
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"lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")
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(define_reservation "VSU_power8"
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"vsu0_power8|vsu1_power8")
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; LS Unit
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(define_insn_reservation "power8-load" 3
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,LU_or_LSU_power8")
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(define_insn_reservation "power8-load-update" 3
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(and (eq_attr "type" "load_u,load_ux")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
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(define_insn_reservation "power8-load-ext" 3
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(and (eq_attr "type" "load_ext")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
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(define_insn_reservation "power8-load-ext-update" 3
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(and (eq_attr "type" "load_ext_u,load_ext_ux")
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(eq_attr "cpu" "power8"))
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"DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
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(define_insn_reservation "power8-fpload" 5
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(and (eq_attr "type" "fpload,vecload")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,LU_power8")
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(define_insn_reservation "power8-fpload-update" 5
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(and (eq_attr "type" "fpload_u,fpload_ux")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,LU_power8+FXU_power8")
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(define_insn_reservation "power8-store" 5 ; store-forwarding latency
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(and (eq_attr "type" "store,store_u")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,LSU_power8+LU_power8")
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(define_insn_reservation "power8-store-update-indexed" 5
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(and (eq_attr "type" "store_ux")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,LSU_power8+LU_power8")
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(define_insn_reservation "power8-fpstore" 5
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,LSU_power8+VSU_power8")
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(define_insn_reservation "power8-fpstore-update" 5
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(and (eq_attr "type" "fpstore_u,fpstore_ux")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,LSU_power8+VSU_power8")
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(define_insn_reservation "power8-vecstore" 5
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,LSU_power8+VSU_power8")
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(define_insn_reservation "power8-larx" 3
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(and (eq_attr "type" "load_l")
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(eq_attr "cpu" "power8"))
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"DU_both_power8,LU_or_LSU_power8")
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(define_insn_reservation "power8-stcx" 10
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(and (eq_attr "type" "store_c")
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(eq_attr "cpu" "power8"))
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"DU_both_power8,LSU_power8+LU_power8")
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(define_insn_reservation "power8-sync" 1
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(and (eq_attr "type" "sync,isync")
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(eq_attr "cpu" "power8"))
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"DU_both_power8,LSU_power8")
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; FX Unit
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(define_insn_reservation "power8-1cyc" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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var_shift_rotate,exts,isel")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,FXU_power8")
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; Extra cycle to LU/LSU
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(define_bypass 2 "power8-1cyc"
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"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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power8-vecstore,power8-larx,power8-stcx")
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; "power8-load,power8-load-update,power8-load-ext,\
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; power8-load-ext-update,power8-fpload,power8-fpload-update,\
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; power8-store,power8-store-update,power8-store-update-indexed,\
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; power8-fpstore,power8-fpstore-update,power8-vecstore,\
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; power8-larx,power8-stcx")
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(define_insn_reservation "power8-2cyc" 2
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(and (eq_attr "type" "cntlz,popcnt")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,FXU_power8")
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(define_insn_reservation "power8-two" 2
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "power8"))
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"DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")
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(define_insn_reservation "power8-three" 3
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "power8"))
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"DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")
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; cmp - Normal compare insns
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(define_insn_reservation "power8-cmp" 2
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(and (eq_attr "type" "cmp")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,FXU_power8")
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; fast_compare : add./and./nor./etc
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(define_insn_reservation "power8-fast-compare" 2
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(and (eq_attr "type" "fast_compare")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,FXU_power8")
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; compare : rldicl./exts./etc
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; delayed_compare : rlwinm./slwi./etc
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; var_delayed_compare : rlwnm./slw./etc
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(define_insn_reservation "power8-compare" 2
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(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
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(eq_attr "cpu" "power8"))
|
||||
"DU_cracked_power8,FXU_power8,FXU_power8")
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; Extra cycle to LU/LSU
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(define_bypass 3 "power8-fast-compare,power8-compare"
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"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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power8-vecstore,power8-larx,power8-stcx")
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; 5 cycle CR latency
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(define_bypass 5 "power8-fast-compare,power8-compare"
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"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
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(define_insn_reservation "power8-mul" 4
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(and (eq_attr "type" "imul,imul2,imul3,lmul")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,FXU_power8")
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(define_insn_reservation "power8-mul-compare" 4
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(and (eq_attr "type" "imul_compare,lmul_compare")
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(eq_attr "cpu" "power8"))
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"DU_cracked_power8,FXU_power8")
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; Extra cycle to LU/LSU
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(define_bypass 5 "power8-mul,power8-mul-compare"
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"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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power8-vecstore,power8-larx,power8-stcx")
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; 7 cycle CR latency
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||||
(define_bypass 7 "power8-mul,power8-mul-compare"
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"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
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; FXU divides are not pipelined
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(define_insn_reservation "power8-idiv" 37
|
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,fxu0_power8*37|fxu1_power8*37")
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|
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(define_insn_reservation "power8-ldiv" 68
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "power8"))
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"DU_any_power8,fxu0_power8*68|fxu1_power8*68")
|
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|
||||
(define_insn_reservation "power8-mtjmpr" 5
|
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(and (eq_attr "type" "mtjmpr")
|
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(eq_attr "cpu" "power8"))
|
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"DU_first_power8,FXU_power8")
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|
||||
; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode
|
||||
(define_insn_reservation "power8-mtcr" 3
|
||||
(and (eq_attr "type" "mtcr")
|
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(eq_attr "cpu" "power8"))
|
||||
"DU_both_power8,FXU_power8")
|
||||
|
||||
|
||||
; CR Unit
|
||||
(define_insn_reservation "power8-mfjmpr" 5
|
||||
(and (eq_attr "type" "mfjmpr")
|
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(eq_attr "cpu" "power8"))
|
||||
"DU_first_power8,cru_power8+FXU_power8")
|
||||
|
||||
(define_insn_reservation "power8-crlogical" 3
|
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(and (eq_attr "type" "cr_logical,delayed_cr")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_first_power8,cru_power8")
|
||||
|
||||
(define_insn_reservation "power8-mfcr" 5
|
||||
(and (eq_attr "type" "mfcr")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_both_power8,cru_power8")
|
||||
|
||||
(define_insn_reservation "power8-mfcrf" 3
|
||||
(and (eq_attr "type" "mfcrf")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_first_power8,cru_power8")
|
||||
|
||||
|
||||
; BR Unit
|
||||
; Branches take dispatch slot 7, but reserve any remaining prior slots to
|
||||
; prevent other insns from grabbing them once this is assigned.
|
||||
(define_insn_reservation "power8-branch" 3
|
||||
(and (eq_attr "type" "jmpreg,branch")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"(du6_power8\
|
||||
|du5_power8+du6_power8\
|
||||
|du4_power8+du5_power8+du6_power8\
|
||||
|du3_power8+du4_power8+du5_power8+du6_power8\
|
||||
|du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
|
||||
|du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
|
||||
|du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\
|
||||
du6_power8),bpu_power8")
|
||||
|
||||
; Branch updating LR/CTR feeding mf[lr|ctr]
|
||||
(define_bypass 4 "power8-branch" "power8-mfjmpr")
|
||||
|
||||
|
||||
; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
|
||||
(define_insn_reservation "power8-fp" 6
|
||||
(and (eq_attr "type" "fp,dmul")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
; Additional 3 cycles for any CR result
|
||||
(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")
|
||||
|
||||
(define_insn_reservation "power8-fpcompare" 8
|
||||
(and (eq_attr "type" "fpcompare")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-sdiv" 27
|
||||
(and (eq_attr "type" "sdiv")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-ddiv" 33
|
||||
(and (eq_attr "type" "ddiv")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-sqrt" 32
|
||||
(and (eq_attr "type" "ssqrt")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-dsqrt" 44
|
||||
(and (eq_attr "type" "dsqrt")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-vecsimple" 2
|
||||
(and (eq_attr "type" "vecperm,vecsimple,veccmp")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-vecnormal" 6
|
||||
(and (eq_attr "type" "vecfloat,vecdouble")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_bypass 7 "power8-vecnormal"
|
||||
"power8-vecsimple,power8-veccomplex,power8-fpstore*,\
|
||||
power8-vecstore")
|
||||
|
||||
(define_insn_reservation "power8-veccomplex" 7
|
||||
(and (eq_attr "type" "veccomplex")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-vecfdiv" 25
|
||||
(and (eq_attr "type" "vecfdiv")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-vecdiv" 31
|
||||
(and (eq_attr "type" "vecdiv")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-mffgpr" 5
|
||||
(and (eq_attr "type" "mffgpr")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-mftgpr" 6
|
||||
(and (eq_attr "type" "mftgpr")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
||||
(define_insn_reservation "power8-crypto" 7
|
||||
(and (eq_attr "type" "crypto")
|
||||
(eq_attr "cpu" "power8"))
|
||||
"DU_any_power8,VSU_power8")
|
||||
|
|
@ -181,7 +181,7 @@ RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
|
|||
POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
|
||||
| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
|
||||
| MASK_VSX | MASK_RECIP_PRECISION | MASK_VSX_TIMODE)
|
||||
RS6000_CPU ("power8", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
|
||||
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
|
||||
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
|
||||
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
|
||||
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
|
||||
|
|
|
@ -24196,7 +24196,8 @@ is_microcoded_insn (rtx insn)
|
|||
if (rs6000_cpu_attr == CPU_CELL)
|
||||
return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
|
||||
|
||||
if (rs6000_sched_groups)
|
||||
if (rs6000_sched_groups
|
||||
&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
|
||||
{
|
||||
enum attr_type type = get_attr_type (insn);
|
||||
if (type == TYPE_LOAD_EXT_U
|
||||
|
@ -24221,7 +24222,8 @@ is_cracked_insn (rtx insn)
|
|||
|| GET_CODE (PATTERN (insn)) == CLOBBER)
|
||||
return false;
|
||||
|
||||
if (rs6000_sched_groups)
|
||||
if (rs6000_sched_groups
|
||||
&& (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
|
||||
{
|
||||
enum attr_type type = get_attr_type (insn);
|
||||
if (type == TYPE_LOAD_U || type == TYPE_STORE_U
|
||||
|
@ -25095,7 +25097,6 @@ insn_must_be_first_in_group (rtx insn)
|
|||
}
|
||||
break;
|
||||
case PROCESSOR_POWER7:
|
||||
case PROCESSOR_POWER8: /* FIXME */
|
||||
type = get_attr_type (insn);
|
||||
|
||||
switch (type)
|
||||
|
@ -25130,6 +25131,39 @@ insn_must_be_first_in_group (rtx insn)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case PROCESSOR_POWER8:
|
||||
type = get_attr_type (insn);
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case TYPE_CR_LOGICAL:
|
||||
case TYPE_DELAYED_CR:
|
||||
case TYPE_MFCR:
|
||||
case TYPE_MFCRF:
|
||||
case TYPE_MTCR:
|
||||
case TYPE_COMPARE:
|
||||
case TYPE_DELAYED_COMPARE:
|
||||
case TYPE_VAR_DELAYED_COMPARE:
|
||||
case TYPE_IMUL_COMPARE:
|
||||
case TYPE_LMUL_COMPARE:
|
||||
case TYPE_SYNC:
|
||||
case TYPE_ISYNC:
|
||||
case TYPE_LOAD_L:
|
||||
case TYPE_STORE_C:
|
||||
case TYPE_LOAD_U:
|
||||
case TYPE_LOAD_UX:
|
||||
case TYPE_LOAD_EXT:
|
||||
case TYPE_LOAD_EXT_U:
|
||||
case TYPE_LOAD_EXT_UX:
|
||||
case TYPE_STORE_UX:
|
||||
case TYPE_VECSTORE:
|
||||
case TYPE_MFJMPR:
|
||||
case TYPE_MTJMPR:
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -25192,7 +25226,6 @@ insn_must_be_last_in_group (rtx insn)
|
|||
}
|
||||
break;
|
||||
case PROCESSOR_POWER7:
|
||||
case PROCESSOR_POWER8: /* FIXME */
|
||||
type = get_attr_type (insn);
|
||||
|
||||
switch (type)
|
||||
|
@ -25209,6 +25242,25 @@ insn_must_be_last_in_group (rtx insn)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case PROCESSOR_POWER8:
|
||||
type = get_attr_type (insn);
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case TYPE_MFCR:
|
||||
case TYPE_MTCR:
|
||||
case TYPE_ISYNC:
|
||||
case TYPE_SYNC:
|
||||
case TYPE_LOAD_L:
|
||||
case TYPE_STORE_C:
|
||||
case TYPE_LOAD_EXT_U:
|
||||
case TYPE_LOAD_EXT_UX:
|
||||
case TYPE_STORE_UX:
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -25298,7 +25350,7 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
|
|||
if (can_issue_more && !is_branch_slot_insn (next_insn))
|
||||
can_issue_more--;
|
||||
|
||||
/* Power6 and Power7 have special group ending nop. */
|
||||
/* Do we have a special group ending nop? */
|
||||
if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
|
||||
|| rs6000_cpu_attr == CPU_POWER8)
|
||||
{
|
||||
|
|
|
@ -213,6 +213,7 @@
|
|||
(include "power5.md")
|
||||
(include "power6.md")
|
||||
(include "power7.md")
|
||||
(include "power8.md")
|
||||
(include "cell.md")
|
||||
(include "xfpu.md")
|
||||
(include "a2.md")
|
||||
|
|
|
@ -60,6 +60,7 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
|
|||
$(srcdir)/config/rs6000/power5.md \
|
||||
$(srcdir)/config/rs6000/power6.md \
|
||||
$(srcdir)/config/rs6000/power7.md \
|
||||
$(srcdir)/config/rs6000/power8.md \
|
||||
$(srcdir)/config/rs6000/cell.md \
|
||||
$(srcdir)/config/rs6000/xfpu.md \
|
||||
$(srcdir)/config/rs6000/a2.md \
|
||||
|
|
Loading…
Reference in New Issue