aarch64: Reimplement vshrn_n* intrinsics using builtins
This patch reimplements the vshrn_n* intrinsics to use RTL builtins.
These perform a narrowing right shift.
Although the intrinsic generates the half-width mode (e.g. V8HI ->
V8QI), the new pattern generates a full 128-bit mode (V8HI -> V16QI) by representing the
fill-with-zeroes semantics of the SHRN instruction. The narrower (V8QI) result is extracted with a
lowpart subreg.
I found this allows the RTL optimisers to do a better job at optimising
redundant moves away in frequently-occurring SHRN+SRHN2 pairs, like in:
uint8x16_t
foo (uint16x8_t in1, uint16x8_t in2)
{
uint8x8_t tmp = vshrn_n_u16 (in2, 7);
uint8x16_t tmp2 = vshrn_high_n_u16 (tmp, in1, 4);
return tmp2;
}
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (shrn): Define
builtin.
* config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le):
Define.
(aarch64_shrn<mode>_insn_be): Likewise.
(aarch64_shrn<mode>): Likewise.
* config/aarch64/arm_neon.h (vshrn_n_s16): Reimplement using
builtins.
(vshrn_n_s32): Likewise.
(vshrn_n_s64): Likewise.
(vshrn_n_u16): Likewise.
(vshrn_n_u32): Likewise.
(vshrn_n_u64): Likewise.
* config/aarch64/iterators.md (vn_mode): New mode attribute.
This commit is contained in:
Kyrylo Tkachov
parent
f7a6d314e7
commit
fdb904a182
@ -188,6 +188,9 @@
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/* Implemented by aarch64_mls_n<mode>. */
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BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE)
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/* Implemented by aarch64_shrn<mode>". */
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BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE)
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/* Implemented by aarch64_<su>mlsl<mode>. */
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BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE)
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BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE)
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@ -1679,6 +1679,56 @@
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DONE;
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})
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(define_insn "aarch64_shrn<mode>_insn_le"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(truncate:<VNARROWQ>
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(lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w")
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(match_operand:VQN 2 "aarch64_simd_rshift_imm")))
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(match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")))]
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"shrn\\t%0.<Vntype>, %1.<Vtype>, %2"
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[(set_attr "type" "neon_shift_imm_narrow_q")]
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)
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(define_insn "aarch64_shrn<mode>_insn_be"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")
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(truncate:<VNARROWQ>
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(lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w")
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(match_operand:VQN 2 "aarch64_simd_rshift_imm")))))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"shrn\\t%0.<Vntype>, %1.<Vtype>, %2"
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[(set_attr "type" "neon_shift_imm_narrow_q")]
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)
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(define_expand "aarch64_shrn<mode>"
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[(set (match_operand:<VNARROWQ> 0 "register_operand")
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(truncate:<VNARROWQ>
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(lshiftrt:VQN (match_operand:VQN 1 "register_operand")
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(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
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"TARGET_SIMD"
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{
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operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
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INTVAL (operands[2]));
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rtx tmp = gen_reg_rtx (<VNARROWQ2>mode);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_shrn<mode>_insn_be (tmp, operands[1],
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operands[2], CONST0_RTX (<VNARROWQ>mode)));
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else
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emit_insn (gen_aarch64_shrn<mode>_insn_le (tmp, operands[1],
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operands[2], CONST0_RTX (<VNARROWQ>mode)));
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/* The intrinsic expects a narrow result, so emit a subreg that will get
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optimized away as appropriate. */
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emit_move_insn (operands[0], lowpart_subreg (<VNARROWQ>mode, tmp,
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<VNARROWQ2>mode));
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DONE;
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}
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)
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;; For quads.
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(define_insn "vec_pack_trunc_<mode>"
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@ -8584,6 +8584,47 @@ vmovn_u64 (uint64x2_t __a)
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return (uint32x2_t) __builtin_aarch64_xtnv2di ((int64x2_t) __a);
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}
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__extension__ extern __inline int8x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_s16 (int16x8_t __a, const int __b)
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{
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return __builtin_aarch64_shrnv8hi (__a, __b);
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}
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__extension__ extern __inline int16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_s32 (int32x4_t __a, const int __b)
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{
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return __builtin_aarch64_shrnv4si (__a, __b);
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}
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_s64 (int64x2_t __a, const int __b)
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{
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return __builtin_aarch64_shrnv2di (__a, __b);
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}
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__extension__ extern __inline uint8x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_u16 (uint16x8_t __a, const int __b)
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{
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return (uint8x8_t)__builtin_aarch64_shrnv8hi ((int16x8_t)__a, __b);
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}
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__extension__ extern __inline uint16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_u32 (uint32x4_t __a, const int __b)
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{
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return (uint16x4_t)__builtin_aarch64_shrnv4si ((int32x4_t)__a, __b);
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}
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__extension__ extern __inline uint32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_n_u64 (uint64x2_t __a, const int __b)
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{
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return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b);
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}
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#define vmull_high_lane_s16(a, b, c) \
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__extension__ \
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({ \
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@ -9858,78 +9899,6 @@ vrsqrteq_u32 (uint32x4_t __a)
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result; \
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})
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#define vshrn_n_s16(a, b) \
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__extension__ \
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({ \
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int16x8_t a_ = (a); \
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int8x8_t result; \
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__asm__ ("shrn %0.8b,%1.8h,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vshrn_n_s32(a, b) \
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__extension__ \
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({ \
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int32x4_t a_ = (a); \
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int16x4_t result; \
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__asm__ ("shrn %0.4h,%1.4s,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vshrn_n_s64(a, b) \
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__extension__ \
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({ \
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int64x2_t a_ = (a); \
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int32x2_t result; \
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__asm__ ("shrn %0.2s,%1.2d,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vshrn_n_u16(a, b) \
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__extension__ \
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({ \
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uint16x8_t a_ = (a); \
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uint8x8_t result; \
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__asm__ ("shrn %0.8b,%1.8h,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vshrn_n_u32(a, b) \
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__extension__ \
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({ \
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uint32x4_t a_ = (a); \
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uint16x4_t result; \
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__asm__ ("shrn %0.4h,%1.4s,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vshrn_n_u64(a, b) \
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__extension__ \
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({ \
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uint64x2_t a_ = (a); \
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uint32x2_t result; \
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__asm__ ("shrn %0.2s,%1.2d,%2" \
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: "=w"(result) \
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: "w"(a_), "i"(b) \
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: /* No clobbers */); \
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result; \
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})
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#define vsli_n_p8(a, b, c) \
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__extension__ \
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({ \
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@ -1458,6 +1458,9 @@
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(QI "qi") (HI "hi")
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(SI "si")])
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;; Like ve_mode but for the half-width modes.
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(define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")])
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;; Vm for lane instructions is restricted to FP_LO_REGS.
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(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
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(V2SI "w") (V4SI "w") (SI "w")])
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