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[RS6000] Change maddld match_operand from DI to GPR 

From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows:
64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits,
and add them together.

We only apply it to 64-bit mode (DI) when implementing maddld.  However, if we
can guarantee that the result of the maddld operation will be limited to 32-bit
mode (SI), we can still apply it to 32-bit mode (SI).

gcc/ChangeLog
2019-06-26  Li Jia He  <helijia@linux.ibm.com>

	* config/rs6000/rs6000.h (TARGET_MADDLD): Remove the restriction of
	TARGET_POWERPC64.
	* config/rs6000/rs6000.md (maddld): Change maddld match_operand from DI
	to GPR.

gcc/testsuite/ChangeLog
2019-06-26  Li Jia He  <helijia@linux.ibm.com>

	* gcc.target/powerpc/maddld-1.c: New testcase.

From-SVN: r272673
This commit is contained in:
Li Jia He 2019-06-26 08:23:06 +00:00 committed by Li Jia He
parent de80936dbf
commit fdfbed383e
5 changed files with 38 additions and 6 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2019-06-26 Li Jia He <helijia@linux.ibm.com>
* config/rs6000/rs6000.h (TARGET_MADDLD): Remove the restriction of
TARGET_POWERPC64.
* config/rs6000/rs6000.md (maddld): Change maddld match_operand from DI
to GPR.
2019-06-26 Segher Boessenkool <segher@kernel.crashing.org>
* doc/invoke.texi (Warning Options): Fix some @opindex syntax.

2
gcc/config/rs6000/rs6000.h
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@ -453,7 +453,7 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POPCNTD
#define TARGET_CTZ TARGET_MODULO
#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_MADDLD TARGET_MODULO
#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)

10
gcc/config/rs6000/rs6000.md
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@ -3062,11 +3062,11 @@
DONE;
})
(define_insn "*maddld4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "gpc_reg_operand" "r"))
(match_operand:DI 3 "gpc_reg_operand" "r")))]
(define_insn "*maddld<mode>4"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r"))
(match_operand:GPR 3 "gpc_reg_operand" "r")))]
"TARGET_MADDLD"
"maddld %0,%1,%2,%3"
[(set_attr "type" "mul")])

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2019-06-26 Li Jia He <helijia@linux.ibm.com>
* gcc.target/powerpc/maddld-1.c: New testcase.
2019-06-06 Hongtao Liu <hongtao.liu@intel.com>
Olga Makhotina <olga.makhotina@intel.com>

21
gcc/testsuite/gcc.target/powerpc/maddld-1.c Normal file
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@ -0,0 +1,21 @@
/* { dg-do compile } */
/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
/* This file tests the maddld instruction can be used in SI mode
on power9 machine. */
int
s_madd (int a, int b, int c)
{
return (a * b) + c;
}
unsigned int
u_madd (unsigned int a, unsigned int b, unsigned int c)
{
return (a * b) + c;
}
/* { dg-final { scan-assembler-times {\mmaddld\s} 2 } } */
/* { dg-final { scan-assembler-not {\mmul} } } */
/* { dg-final { scan-assembler-not {\madd} } } */