optc-gen.awk: Handle stand-alone Mask records.
* optc-gen.awk: Handle stand-alone Mask records. * opth-gen.awk: Likewise. * doc/options.texi (Option file format): Document them. * config.gcc (sparc-*-netbsdelf*, sparc-*-linux*, sparc64-*-freebsd*, sparc64-*-linux*, sparc64-*-netbsd*): Add long-double-switch.opt. (sparc64-*-openbsd*, sparc64-*-elf*): Add little-endian.opt. * config/sparc/sparc.h (MASK_FPU, MASK_UNALIGNED_DOUBLES, MASK_V8, MASK_SPARCLITE, MASK_SPARCLET, MASK_V9, MASK_DEPRECATED_V8_INSNS, MASK_IMPURE_TEXT, MASK_APP_REGS, MASK_HARD_QUAD, MASK_LITTLE_ENDIAN, MASK_PTR64, MASK_64BIT, MASK_STACK_BIAS, MASK_FPU_SET, MASK_VIS, MASK_V8PLUS, MASK_FASTER_STRUCTS, MASK_LONG_DOUBLE_128): Delete. (TARGET_FPU, TARGET_UNALIGNED_DOUBLES, TARGET_V8, TARGET_SPARCLITE, TARGET_SPARCLET, TARGET_V9, TARGET_DEPRECATED_V8_INSNS, TARGET_IMPURE_TEXT, TARGET_APP_REGS, MASK_HARD_QUAD, TARGET_LITTLE_ENDIAN, TARGET_PTR64, TARGET_64BIT, MASK_STACK_BIAS, TARGET_FPU_SET, TARGET_VIS, TARGET_V8PLUS, TARGET_FASTER_STRUCTS, TARGET_LONG_DOUBLE_128): Likewise. (TARGET_SWITCHES, SUBTARGET_SWITCHES): Likewise. (TARGET_OPTIONS, SUBTARGET_OPTIONS): Likewise. * config/sparc/freebsd.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/linux.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/linux64.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/netbsd-elf.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/sp64-elf.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/sparc.c (fpu_option_set): New global. (sparc_handle_option): New function. (sparc_override_options): Test fpu_option_set. (TARGET_DEFAULT_TARGET_FLAGS): Set to TARGET_DEFAULT. (TARGET_HANDLE_OPTION): Set to sparc_handle_option. * config/sparc/sparc.opt: New file. * config/sparc/little-endian.opt: Likewise. * config/sparc/long-double-switch.opt: Likewise. From-SVN: r98078
This commit is contained in:
Eric Botcazou
parent
c8de0f3bab
commit
fe609b0fdf
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@ -1924,6 +1924,7 @@ sh-*-*)
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;;
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sparc-*-netbsdelf*)
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tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
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extra_options="${extra_options} sparc/long-double-switch.opt"
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;;
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sparc-*-openbsd*)
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tm_defines=OBSD_OLD_GAS
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@ -1935,6 +1936,7 @@ sparc-*-openbsd*)
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;;
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sparc64-*-openbsd*)
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tm_file="sparc/openbsd1-64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sp64-elf.h openbsd.h sparc/openbsd64.h"
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extra_options="${extra_options} sparc/little-endian.opt"
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gas=yes gnu_ld=yes
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with_cpu=ultrasparc
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;;
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@ -1946,6 +1948,7 @@ sparc-*-elf*)
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;;
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sparc-*-linux*) # SPARC's running GNU/Linux, libc6
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tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h"
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extra_options="${extra_options} sparc/long-double-switch.opt"
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tmake_file="${tmake_file} sparc/t-crtfm"
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;;
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sparc-*-rtems*)
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@ -2044,12 +2047,14 @@ sparc-*-sysv4*)
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;;
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sparc64-*-elf*)
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tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sp64-elf.h"
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extra_options="${extra_options} sparc/little-endian.opt"
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tmake_file="${tmake_file} sparc/t-crtfm"
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extra_parts="crtbegin.o crtend.o"
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use_fixproto=yes
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;;
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sparc64-*-freebsd*|ultrasparc-*-freebsd*)
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tm_file="${tm_file} ${fbsd_tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/freebsd.h"
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extra_options="${extra_options} sparc/long-double-switch.opt"
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tmake_file="${tmake_file} sparc/t-crtfm"
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case "x$with_cpu" in
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xultrasparc) ;;
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@ -2059,13 +2064,15 @@ sparc64-*-freebsd*|ultrasparc-*-freebsd*)
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need_64bit_hwint=yes
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;;
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sparc64-*-linux*) # 64-bit SPARC's running GNU/Linux
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tmake_file="${tmake_file} sparc/t-linux64 sparc/t-crtfm"
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tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux64.h"
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extra_options="${extra_options} sparc/long-double-switch.opt"
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tmake_file="${tmake_file} sparc/t-linux64 sparc/t-crtfm"
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;;
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sparc64-*-netbsd*)
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tmake_file="${tmake_file} sparc/t-netbsd64"
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tm_file="sparc/biarch64.h ${tm_file}"
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tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
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extra_options="${extra_options} sparc/long-double-switch.opt"
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tmake_file="${tmake_file} sparc/t-netbsd64"
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;;
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strongarm-*-elf*)
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tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
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@ -72,11 +72,6 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Definitions for 64-bit SPARC running systems with ELF. */
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
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{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
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#undef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (FreeBSD/sparc64 ELF)");
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@ -86,11 +86,6 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)");
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
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{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
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#undef SIZE_TYPE
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#define SIZE_TYPE "unsigned int"
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@ -106,11 +106,6 @@ Boston, MA 02111-1307, USA. */
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#undef SPARC_DEFAULT_CMODEL
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#define SPARC_DEFAULT_CMODEL CM_MEDLOW
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
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{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
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#undef WCHAR_TYPE
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#define WCHAR_TYPE "int"
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@ -0,0 +1,28 @@
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; Options for the SPARC port of the compiler
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;
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; Copyright (C) 2005 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 2, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING. If not, write to the Free
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; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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; 02111-1307, USA.
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mlittle-endian
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Target Report RejectNegative Mask(LITTLE_ENDIAN) MaskExists
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Generate code for little-endian
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mbig-endian
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Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
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Generate code for big-endian
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@ -0,0 +1,28 @@
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; Options for the SPARC port of the compiler
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;
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; Copyright (C) 2005 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 2, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING. If not, write to the Free
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; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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; 02111-1307, USA.
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mlong-double-128
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Target Report RejectNegative Mask(LONG_DOUBLE_128) MaskExists
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Use 128-bit long double
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mlong-double-64
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Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
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Use 64-bit long double
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@ -195,13 +195,6 @@ Boston, MA 02111-1307, USA. */
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{ "netbsd_entry_point", NETBSD_ENTRY_POINT },
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/* What extra switches do we need? */
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
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{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
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/* Build a compiler that supports -m32 and -m64? */
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#ifdef SPARC_BI_ARCH
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@ -81,12 +81,6 @@ crtbegin.o%s \
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|| (CHAR) == 'h' \
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|| (CHAR) == 'z')
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/* V9 chips can handle either endianness. */
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \
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{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") },
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#undef BYTES_BIG_ENDIAN
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#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
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@ -299,6 +299,7 @@ static HOST_WIDE_INT frame_base_offset;
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/* 1 if the next opcode is to be specially indented. */
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int sparc_indent_opcode = 0;
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static bool sparc_handle_option (size_t, const char *, int);
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static void sparc_init_modes (void);
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static void scan_record_type (tree, int *, int *, int *);
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static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
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@ -372,6 +373,7 @@ const struct attribute_spec sparc_attribute_table[];
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/* Code model option as passed by user. */
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const char *sparc_cmodel_string;
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/* Parsed value. */
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enum cmodel sparc_cmodel;
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@ -388,7 +390,10 @@ struct sparc_cpu_select sparc_select[] =
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/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
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enum processor_type sparc_cpu;
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/* Whether an FPU option was specified. */
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static bool fpu_option_set = false;
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/* Initialize the GCC target structure. */
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/* The sparc default is to use .half rather than .short for aligned
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@ -506,11 +511,45 @@ enum processor_type sparc_cpu;
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
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#undef TARGET_DEFAULT_TARGET_FLAGS
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#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
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#undef TARGET_HANDLE_OPTION
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#define TARGET_HANDLE_OPTION sparc_handle_option
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#undef TARGET_ASM_FILE_END
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#define TARGET_ASM_FILE_END sparc_file_end
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Implement TARGET_HANDLE_OPTION. */
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static bool
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sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
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{
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switch (code)
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{
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case OPT_mfpu:
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case OPT_mhard_float:
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case OPT_msoft_float:
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fpu_option_set = true;
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break;
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case OPT_mcpu_:
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sparc_select[1].string = arg;
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break;
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case OPT_mtune_:
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sparc_select[2].string = arg;
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break;
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case OPT_mcmodel_:
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sparc_cmodel_string = arg;
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break;
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}
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return true;
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}
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/* Validate and override various options, and do some machine dependent
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initialization. */
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@ -657,13 +696,9 @@ sparc_override_options (void)
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}
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/* If -mfpu or -mno-fpu was explicitly used, don't override with
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the processor default. Clear MASK_FPU_SET to avoid confusing
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the reverse mapping from switch values to names. */
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if (TARGET_FPU_SET)
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{
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target_flags = (target_flags & ~MASK_FPU) | fpu;
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target_flags &= ~MASK_FPU_SET;
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}
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the processor default. */
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if (fpu_option_set)
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target_flags = (target_flags & ~MASK_FPU) | fpu;
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/* Don't allow -mvis if FPU is disabled. */
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if (! TARGET_FPU)
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@ -483,122 +483,14 @@ extern enum cmodel sparc_cmodel;
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/* Show we can debug even without a frame pointer. */
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#define CAN_DEBUG_WITHOUT_FP
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/* Option handling. */
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#define OVERRIDE_OPTIONS sparc_override_options ()
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/* Run-time compilation parameters selecting different hardware subsets. */
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extern int target_flags;
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/* Nonzero if we should generate code to use the fpu. */
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#define MASK_FPU 1
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#define TARGET_FPU (target_flags & MASK_FPU)
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/* Nonzero if we should assume that double pointers might be unaligned.
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This can happen when linking gcc compiled code with other compilers,
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because the ABI only guarantees 4 byte alignment. */
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#define MASK_UNALIGNED_DOUBLES 4
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#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
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/* Nonzero means that we should generate code for a v8 sparc. */
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#define MASK_V8 0x8
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#define TARGET_V8 (target_flags & MASK_V8)
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/* Nonzero means that we should generate code for a sparclite.
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This enables the sparclite specific instructions, but does not affect
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whether FPU instructions are emitted. */
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#define MASK_SPARCLITE 0x10
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#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
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/* Nonzero if we're compiling for the sparclet. */
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#define MASK_SPARCLET 0x20
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#define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
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/* Nonzero if we're compiling for v9 sparc.
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Note that v9's can run in 32 bit mode so this doesn't necessarily mean
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the word size is 64. */
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#define MASK_V9 0x40
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#define TARGET_V9 (target_flags & MASK_V9)
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/* Nonzero to generate code that uses the instructions deprecated in
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the v9 architecture. This option only applies to v9 systems. */
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/* ??? This isn't user selectable yet. It's used to enable such insns
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on 32 bit v9 systems and for the moment they're permanently disabled
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on 64 bit v9 systems. */
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#define MASK_DEPRECATED_V8_INSNS 0x80
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#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
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/* Mask of all CPU selection flags. */
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#define MASK_ISA \
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(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
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/* Nonzero means don't pass `-assert pure-text' to the linker. */
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#define MASK_IMPURE_TEXT 0x100
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#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
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/* 0x200 is unused */
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/* Nonzero means use the registers that the SPARC ABI reserves for
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application software. This must be the default to coincide with the
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setting in FIXED_REGISTERS. */
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#define MASK_APP_REGS 0x400
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#define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
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/* Option to select how quad word floating point is implemented.
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When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
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Otherwise, we use the SPARC ABI quad library functions. */
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#define MASK_HARD_QUAD 0x800
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#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
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/* Nonzero on little-endian machines. */
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/* ??? Little endian support currently only exists for sparc86x-elf and
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sparc64-elf configurations. May eventually want to expand the support
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to all targets, but for now it's kept local to only those two. */
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#define MASK_LITTLE_ENDIAN 0x1000
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#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
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/* 0x2000, 0x4000 are unused */
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/* Nonzero if pointers are 64 bits. */
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#define MASK_PTR64 0x8000
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#define TARGET_PTR64 (target_flags & MASK_PTR64)
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/* Nonzero if generating code to run in a 64 bit environment.
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This is intended to only be used by TARGET_ARCH{32,64} as they are the
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mechanism used to control compile time or run time selection. */
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#define MASK_64BIT 0x10000
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#define TARGET_64BIT (target_flags & MASK_64BIT)
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/* 0x20000,0x40000 unused */
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/* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
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adding 2047 to %sp. This option is for v9 only and is the default. */
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#define MASK_STACK_BIAS 0x80000
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#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
|
||||
|
||||
/* 0x100000,0x200000 unused */
|
||||
|
||||
/* Nonzero means -m{,no-}fpu was passed on the command line. */
|
||||
#define MASK_FPU_SET 0x400000
|
||||
#define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
|
||||
|
||||
/* Use the UltraSPARC Visual Instruction Set extensions. */
|
||||
#define MASK_VIS 0x1000000
|
||||
#define TARGET_VIS (target_flags & MASK_VIS)
|
||||
|
||||
/* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
|
||||
the current out and global registers and Linux 2.2+ as well. */
|
||||
#define MASK_V8PLUS 0x2000000
|
||||
#define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
|
||||
|
||||
/* Force a the fastest alignment on structures to take advantage of
|
||||
faster copies. */
|
||||
#define MASK_FASTER_STRUCTS 0x4000000
|
||||
#define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
|
||||
|
||||
/* Use IEEE quad long double. */
|
||||
#define MASK_LONG_DOUBLE_128 0x8000000
|
||||
#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
|
||||
|
||||
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
|
||||
TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
|
||||
to get high 32 bits. False in V8+ or V9 because multiply stores
|
||||
|
|
@ -613,79 +505,11 @@ extern int target_flags;
|
|||
(TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
|
||||
|| TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
|
||||
|
||||
|
||||
/* Macro to define tables used to set the flags.
|
||||
This is a list in braces of pairs in braces,
|
||||
each pair being { "NAME", VALUE }
|
||||
where VALUE is the bits to set or minus the bits to clear.
|
||||
An empty string NAME is used to identify the default VALUE. */
|
||||
|
||||
#define TARGET_SWITCHES \
|
||||
{ {"fpu", MASK_FPU | MASK_FPU_SET, \
|
||||
N_("Use hardware fp") }, \
|
||||
{"no-fpu", -MASK_FPU, \
|
||||
N_("Do not use hardware fp") }, \
|
||||
{"no-fpu", MASK_FPU_SET, NULL, }, \
|
||||
{"hard-float", MASK_FPU | MASK_FPU_SET, \
|
||||
N_("Use hardware fp") }, \
|
||||
{"soft-float", -MASK_FPU, \
|
||||
N_("Do not use hardware fp") }, \
|
||||
{"soft-float", MASK_FPU_SET, NULL }, \
|
||||
{"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
|
||||
N_("Assume possible double misalignment") }, \
|
||||
{"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
|
||||
N_("Assume all doubles are aligned") }, \
|
||||
{"impure-text", MASK_IMPURE_TEXT, \
|
||||
N_("Pass -assert pure-text to linker") }, \
|
||||
{"no-impure-text", -MASK_IMPURE_TEXT, \
|
||||
N_("Do not pass -assert pure-text to linker") }, \
|
||||
{"app-regs", MASK_APP_REGS, \
|
||||
N_("Use ABI reserved registers") }, \
|
||||
{"no-app-regs", -MASK_APP_REGS, \
|
||||
N_("Do not use ABI reserved registers") }, \
|
||||
{"hard-quad-float", MASK_HARD_QUAD, \
|
||||
N_("Use hardware quad fp instructions") }, \
|
||||
{"soft-quad-float", -MASK_HARD_QUAD, \
|
||||
N_("Do not use hardware quad fp instructions") }, \
|
||||
{"v8plus", MASK_V8PLUS, \
|
||||
N_("Compile for v8plus ABI") }, \
|
||||
{"no-v8plus", -MASK_V8PLUS, \
|
||||
N_("Do not compile for v8plus ABI") }, \
|
||||
{"vis", MASK_VIS, \
|
||||
N_("Utilize Visual Instruction Set") }, \
|
||||
{"no-vis", -MASK_VIS, \
|
||||
N_("Do not utilize Visual Instruction Set") }, \
|
||||
{"ptr64", MASK_PTR64, \
|
||||
N_("Pointers are 64-bit") }, \
|
||||
{"ptr32", -MASK_PTR64, \
|
||||
N_("Pointers are 32-bit") }, \
|
||||
{"32", -MASK_64BIT, \
|
||||
N_("Use 32-bit ABI") }, \
|
||||
{"64", MASK_64BIT, \
|
||||
N_("Use 64-bit ABI") }, \
|
||||
{"stack-bias", MASK_STACK_BIAS, \
|
||||
N_("Use stack bias") }, \
|
||||
{"no-stack-bias", -MASK_STACK_BIAS, \
|
||||
N_("Do not use stack bias") }, \
|
||||
{"faster-structs", MASK_FASTER_STRUCTS, \
|
||||
N_("Use structs on stronger alignment for double-word copies") }, \
|
||||
{"no-faster-structs", -MASK_FASTER_STRUCTS, \
|
||||
N_("Do not use structs on stronger alignment for double-word copies") }, \
|
||||
{"relax", 0, \
|
||||
N_("Optimize tail call instructions in assembler and linker") }, \
|
||||
{"no-relax", 0, \
|
||||
N_("Do not optimize tail call instructions in assembler or linker") }, \
|
||||
SUBTARGET_SWITCHES \
|
||||
{ "", TARGET_DEFAULT, ""}}
|
||||
|
||||
/* MASK_APP_REGS must always be the default because that's what
|
||||
FIXED_REGISTERS is set to and -ffixed- is processed before
|
||||
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
|
||||
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
|
||||
|
||||
/* This is meant to be redefined in target specific files. */
|
||||
#define SUBTARGET_SWITCHES
|
||||
|
||||
/* Processor type.
|
||||
These must match the values for the cpu attribute in sparc.md. */
|
||||
enum processor_type {
|
||||
|
|
@ -712,20 +536,6 @@ extern enum processor_type sparc_cpu;
|
|||
Every file includes us, but not every file includes insn-attr.h. */
|
||||
#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
|
||||
|
||||
#define TARGET_OPTIONS \
|
||||
{ \
|
||||
{ "cpu=", &sparc_select[1].string, \
|
||||
N_("Use features of and schedule code for given CPU"), 0}, \
|
||||
{ "tune=", &sparc_select[2].string, \
|
||||
N_("Schedule code for given CPU"), 0}, \
|
||||
{ "cmodel=", &sparc_cmodel_string, \
|
||||
N_("Use given SPARC code model"), 0}, \
|
||||
SUBTARGET_OPTIONS \
|
||||
}
|
||||
|
||||
/* This is meant to be redefined in target specific files. */
|
||||
#define SUBTARGET_OPTIONS
|
||||
|
||||
/* Support for a compile-time default CPU, et cetera. The rules are:
|
||||
--with-cpu is ignored if -mcpu is specified.
|
||||
--with-tune is ignored if -mtune is specified.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
; Options for the SPARC port of the compiler
|
||||
;
|
||||
; Copyright (C) 2005 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 2, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
; License for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING. If not, write to the Free
|
||||
; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
; 02111-1307, USA.
|
||||
|
||||
mfpu
|
||||
Target Report Mask(FPU)
|
||||
Use hardware FP
|
||||
|
||||
mhard-float
|
||||
Target RejectNegative Mask(FPU) MaskExists
|
||||
Use hardware FP
|
||||
|
||||
msoft-float
|
||||
Target RejectNegative InverseMask(FPU)
|
||||
Do not use hardware FP
|
||||
|
||||
munaligned-doubles
|
||||
Target Report Mask(UNALIGNED_DOUBLES)
|
||||
Assume possible double misalignment
|
||||
|
||||
mimpure-text
|
||||
Target Report
|
||||
Pass -assert pure-text to linker
|
||||
|
||||
mapp-regs
|
||||
Target Report Mask(APP_REGS)
|
||||
Use ABI reserved registers
|
||||
|
||||
mhard-quad-float
|
||||
Target Report RejectNegative Mask(HARD_QUAD)
|
||||
Use hardware quad FP instructions
|
||||
|
||||
msoft-quad-float
|
||||
Target Report RejectNegative InverseMask(HARD_QUAD)
|
||||
Do not use hardware quad fp instructions
|
||||
|
||||
mv8plus
|
||||
Target Report Mask(V8PLUS)
|
||||
Compile for V8+ ABI
|
||||
|
||||
mvis
|
||||
Target Report Mask(VIS)
|
||||
Use UltraSPARC Visual Instruction Set extensions
|
||||
|
||||
mptr64
|
||||
Target Report RejectNegative Mask(PTR64)
|
||||
Pointers are 64-bit
|
||||
|
||||
mptr32
|
||||
Target Report RejectNegative InverseMask(PTR64)
|
||||
Pointers are 32-bit
|
||||
|
||||
m64
|
||||
Target Report RejectNegative Mask(64BIT)
|
||||
Use 64-bit ABI
|
||||
|
||||
m32
|
||||
Target Report RejectNegative InverseMask(64BIT)
|
||||
Use 32-bit ABI
|
||||
|
||||
mstack-bias
|
||||
Target Report Mask(STACK_BIAS)
|
||||
Use stack bias
|
||||
|
||||
mfaster-structs
|
||||
Target Report Mask(FASTER_STRUCTS)
|
||||
Use structs on stronger alignment for double-word copies
|
||||
|
||||
mrelax
|
||||
Target
|
||||
Optimize tail call instructions in assembler and linker
|
||||
|
||||
mcpu=
|
||||
Target RejectNegative Joined
|
||||
Use features of and schedule code for given CPU
|
||||
|
||||
mtune=
|
||||
Target RejectNegative Joined
|
||||
Schedule code for given CPU
|
||||
|
||||
mcmodel=
|
||||
Target RejectNegative Joined
|
||||
Use given SPARC-V9 code model
|
||||
|
||||
|
||||
Mask(LITTLE_ENDIAN)
|
||||
;; Generate code for little-endian
|
||||
|
||||
Mask(LONG_DOUBLE_128)
|
||||
;; Use 128-bit long double
|
||||
|
||||
Mask(SPARCLITE)
|
||||
;; Generate code for SPARClite
|
||||
|
||||
Mask(SPARCLET)
|
||||
;; Generate code for SPARClet
|
||||
|
||||
Mask(V8)
|
||||
;; Generate code for SPARC-V8
|
||||
|
||||
Mask(V9)
|
||||
;; Generate code for SPARC-V9
|
||||
|
||||
Mask(DEPRECATED_V8_INSNS)
|
||||
;; Generate code that uses the V8 instructions deprecated
|
||||
;; in the V9 architecture.
|
||||
|
|
@ -25,15 +25,17 @@ blank lines. Comments may appear on their own line anywhere within
|
|||
the file and are preceded by semicolons. Whitespace is allowed before
|
||||
the semicolon.
|
||||
|
||||
The files can contain two types of record: language definitions and
|
||||
option definitions.
|
||||
The files can contain the following types of record:
|
||||
|
||||
A language definition record has two fields: the string
|
||||
@samp{Language} and the name of the language. Once a language has
|
||||
been declared in this way, it can be used as an option property.
|
||||
@itemize @bullet
|
||||
@item
|
||||
A language definition record. These records have two fields: the
|
||||
string @samp{Language} and the name of the language. Once a language
|
||||
has been declared in this way, it can be used as an option property.
|
||||
@xref{Option properties}.
|
||||
|
||||
An option definition record has the following fields:
|
||||
@item
|
||||
An option definition record. These records have the following fields:
|
||||
|
||||
@enumerate
|
||||
@item
|
||||
|
|
@ -59,6 +61,21 @@ used instead of the option's name and the text to the right of the
|
|||
tab forms the help text. This allows you to elaborate on what type
|
||||
of argument the option takes.
|
||||
|
||||
@item
|
||||
A target mask record. These records have one field of the form
|
||||
@samp{Mask(@var{x})}. The options-processing script will automatically
|
||||
allocate a bit in @code{target_flags} (@pxref{Run-time Target}) for
|
||||
each mask name @var{x} and set the macro @code{MASK_@var{x}} to the
|
||||
appropriate bitmask. It will also declare a @code{TARGET_@var{x}}
|
||||
macro that has the value 1 when bit @code{MASK_@var{x}} is set and
|
||||
0 otherwise.
|
||||
|
||||
They are primarily intended to declare target masks that are not
|
||||
associated with user options, either because these masks represent
|
||||
internal switches or because the options are not available on all
|
||||
configurations and yet the masks always need to be defined.
|
||||
@end itemize
|
||||
|
||||
@node Option properties
|
||||
@section Option properties
|
||||
|
||||
|
|
|
|||
|
|
@ -42,10 +42,13 @@ BEGIN {
|
|||
n_langs++;
|
||||
}
|
||||
else {
|
||||
opts[n_opts] = $1
|
||||
flags[n_opts] = $2
|
||||
help[n_opts] = $3
|
||||
n_opts++;
|
||||
name = opt_args("Mask", $1)
|
||||
if (name == "") {
|
||||
opts[n_opts] = $1
|
||||
flags[n_opts] = $2
|
||||
help[n_opts] = $3
|
||||
n_opts++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@
|
|||
BEGIN {
|
||||
n_opts = 0
|
||||
n_langs = 0
|
||||
quote = "\042"
|
||||
n_extra_masks = 0
|
||||
quote = "\042"
|
||||
comma = ","
|
||||
FS=SUBSEP
|
||||
}
|
||||
|
|
@ -38,10 +39,16 @@ BEGIN {
|
|||
n_langs++;
|
||||
}
|
||||
else {
|
||||
opts[n_opts] = $1
|
||||
flags[n_opts] = $2
|
||||
help[n_opts] = $3
|
||||
n_opts++;
|
||||
name = opt_args("Mask", $1)
|
||||
if (name == "") {
|
||||
opts[n_opts] = $1
|
||||
flags[n_opts] = $2
|
||||
help[n_opts] = $3
|
||||
n_opts++;
|
||||
}
|
||||
else {
|
||||
extra_masks[n_extra_masks++] = name
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -54,6 +61,7 @@ print "#ifndef OPTIONS_H"
|
|||
print "#define OPTIONS_H"
|
||||
print ""
|
||||
print "extern int target_flags;"
|
||||
print ""
|
||||
|
||||
for (i = 0; i < n_opts; i++) {
|
||||
name = var_name(flags[i]);
|
||||
|
|
@ -73,6 +81,9 @@ for (i = 0; i < n_opts; i++) {
|
|||
if (name != "" && !flag_set_p("MaskExists", flags[i]))
|
||||
print "#define MASK_" name " (1 << " masknum++ ")"
|
||||
}
|
||||
for (i = 0; i < n_extra_masks; i++) {
|
||||
print "#define MASK_" extra_masks[i] " (1 << " masknum++ ")"
|
||||
}
|
||||
if (masknum > 31)
|
||||
print "#error too many target masks"
|
||||
print ""
|
||||
|
|
@ -83,6 +94,10 @@ for (i = 0; i < n_opts; i++) {
|
|||
print "#define TARGET_" name \
|
||||
" ((target_flags & MASK_" name ") != 0)"
|
||||
}
|
||||
for (i = 0; i < n_extra_masks; i++) {
|
||||
print "#define TARGET_" extra_masks[i] \
|
||||
" ((target_flags & MASK_" extra_masks[i] ") != 0)"
|
||||
}
|
||||
print ""
|
||||
|
||||
for (i = 0; i < n_opts; i++) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue