re PR target/54700 (Optimize away x<0 as mask argument of a blend.)
PR target/54700 * config/i386/sse.md (ssebytemode): Add V16SI, V8SI and V4SI entries. (ssefltmodesuffix, ssefltvecmode): New define_mode_attrs. (*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt, *<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint, *<sse4_1_avx2>_pblendvb_lt): New define_insns. * g++.target/i386/sse4_1-pr54700-1.C: New test. * g++.target/i386/sse4_1-pr54700-2.C: New test. * g++.target/i386/avx-pr54700-1.C: New test. * g++.target/i386/avx-pr54700-2.C: New test. * g++.target/i386/avx2-pr54700-1.C: New test. * g++.target/i386/avx2-pr54700-2.C: New test. * g++.target/i386/sse4_1-check.h: New file. * g++.target/i386/avx-check.h: New file. * g++.target/i386/avx2-check.h: New file. * g++.target/i386/m128-check.h: New file. * g++.target/i386/m256-check.h: New file. * g++.target/i386/avx-os-support.h: New file. From-SVN: r266621
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
f06e47d7b6
commit
fe907c1fd2
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@ -1,5 +1,12 @@
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2018-11-29 Jakub Jelinek <jakub@redhat.com>
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PR target/54700
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* config/i386/sse.md (ssebytemode): Add V16SI, V8SI and V4SI entries.
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(ssefltmodesuffix, ssefltvecmode): New define_mode_attrs.
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(*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt,
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*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint,
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*<sse4_1_avx2>_pblendvb_lt): New define_insns.
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PR target/88152
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* tree.h (build_uniform_cst, uniform_integer_cst_p): Declare.
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* tree.c (build_uniform_cst, uniform_integer_cst_p): New functions.
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@ -601,7 +601,8 @@
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(V4DI "V8DI") (V8DI "V16DI")])
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(define_mode_attr ssebytemode
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[(V8DI "V64QI") (V4DI "V32QI") (V2DI "V16QI")])
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[(V8DI "V64QI") (V4DI "V32QI") (V2DI "V16QI")
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(V16SI "V64QI") (V8SI "V32QI") (V4SI "V16QI")])
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;; All 128bit vector integer modes
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(define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI])
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@ -15681,6 +15682,60 @@
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]
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(const_string "<ssevecmode>")))])
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(define_insn "*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt"
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[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x")
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(unspec:VF_128_256
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[(match_operand:VF_128_256 1 "register_operand" "0,0,x")
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(match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm")
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(subreg:VF_128_256
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(lt:<sseintvecmode>
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(match_operand:<sseintvecmode> 3 "register_operand" "Yz,Yz,x")
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(match_operand:<sseintvecmode> 4 "const0_operand" "C,C,C")) 0)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"@
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blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "ssemov")
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(set_attr "length_immediate" "1")
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(set_attr "prefix_data16" "1,1,*")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "orig,orig,vex")
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(set_attr "btver2_decode" "vector,vector,vector")
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(set_attr "mode" "<MODE>")])
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(define_mode_attr ssefltmodesuffix
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[(V2DI "pd") (V4DI "pd") (V4SI "ps") (V8SI "ps")])
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(define_mode_attr ssefltvecmode
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[(V2DI "V2DF") (V4DI "V4DF") (V4SI "V4SF") (V8SI "V8SF")])
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(define_insn "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
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[(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
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(unspec:<ssebytemode>
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[(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
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(match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
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(subreg:<ssebytemode>
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(lt:VI48_AVX
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(match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
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(match_operand:VI48_AVX 4 "const0_operand" "C,C,C")) 0)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"@
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blendv<ssefltmodesuffix>\t{%3, %2, %0|%0, %2, %3}
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blendv<ssefltmodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vblendv<ssefltmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "ssemov")
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(set_attr "length_immediate" "1")
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(set_attr "prefix_data16" "1,1,*")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "orig,orig,vex")
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(set_attr "btver2_decode" "vector,vector,vector")
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(set_attr "mode" "<ssefltvecmode>")])
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(define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>"
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[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x")
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(unspec:VF_128_256
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@ -15779,6 +15834,27 @@
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(set_attr "btver2_decode" "vector,vector,vector")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*<sse4_1_avx2>_pblendvb_lt"
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[(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x")
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(unspec:VI1_AVX2
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[(match_operand:VI1_AVX2 1 "register_operand" "0,0,x")
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(match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm")
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(lt:VI1_AVX2 (match_operand:VI1_AVX2 3 "register_operand" "Yz,Yz,x")
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(match_operand:VI1_AVX2 4 "const0_operand" "C,C,C"))]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"@
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pblendvb\t{%3, %2, %0|%0, %2, %3}
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pblendvb\t{%3, %2, %0|%0, %2, %3}
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vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "*,*,1")
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(set_attr "prefix" "orig,orig,vex")
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(set_attr "btver2_decode" "vector,vector,vector")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "sse4_1_pblendw"
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[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,x")
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(vec_merge:V8HI
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@ -1,5 +1,19 @@
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2018-11-29 Jakub Jelinek <jakub@redhat.com>
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PR target/54700
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* g++.target/i386/sse4_1-pr54700-1.C: New test.
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* g++.target/i386/sse4_1-pr54700-2.C: New test.
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* g++.target/i386/avx-pr54700-1.C: New test.
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* g++.target/i386/avx-pr54700-2.C: New test.
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* g++.target/i386/avx2-pr54700-1.C: New test.
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* g++.target/i386/avx2-pr54700-2.C: New test.
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* g++.target/i386/sse4_1-check.h: New file.
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* g++.target/i386/avx-check.h: New file.
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* g++.target/i386/avx2-check.h: New file.
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* g++.target/i386/m128-check.h: New file.
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* g++.target/i386/m256-check.h: New file.
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* g++.target/i386/avx-os-support.h: New file.
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PR target/88152
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* g++.dg/tree-ssa/pr88152-1.C: New test.
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* g++.dg/tree-ssa/pr88152-2.C: New test.
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@ -0,0 +1 @@
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#include "../../gcc.target/i386/avx-check.h"
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@ -0,0 +1 @@
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#include "../../gcc.target/i386/avx-os-support.h"
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@ -0,0 +1,9 @@
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/* PR target/54700 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -std=c++14 -mavx -mno-xop -mno-avx2" } */
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/* { dg-final { scan-assembler-not "vpcmpgt\[bdq]" } } */
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/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */
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/* { dg-final { scan-assembler-times "vblendvps" 4 } } */
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/* { dg-final { scan-assembler-times "vblendvpd" 4 } } */
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#include "sse4_1-pr54700-1.C"
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@ -0,0 +1,8 @@
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/* PR target/54700 */
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/* { dg-do run { target avx } } */
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/* { dg-options "-O2 -std=c++14 -mavx -mno-xop -mno-avx2" } */
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#define CHECK_H "avx-check.h"
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#define TEST avx_test
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#include "sse4_1-pr54700-2.C"
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#include "../../gcc.target/i386/avx2-check.h"
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/* PR target/54700 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -std=c++14 -mavx2 -mno-xop -mno-avx512f" } */
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/* { dg-final { scan-assembler-not "vpcmpgt\[bdq]" } } */
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/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */
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/* { dg-final { scan-assembler-times "vblendvps" 4 } } */
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/* { dg-final { scan-assembler-times "vblendvpd" 4 } } */
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#include <x86intrin.h>
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__attribute__((noipa)) __v32qi
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f1 (__v32qi a, __v32qi b, __v32qi c)
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{
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return a < 0 ? b : c;
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}
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__attribute__((noipa)) __v32qi
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f2 (__v32qi a, __v32qi b, __v32qi c)
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{
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return a >= 0 ? b : c;
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}
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__attribute__((noipa)) __v8si
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f3 (__v8si a, __v8si b, __v8si c)
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{
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return a < 0 ? b : c;
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}
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__attribute__((noipa)) __v8si
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f4 (__v8si a, __v8si b, __v8si c)
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{
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return a >= 0 ? b : c;
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}
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__attribute__((noipa)) __v4di
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f5 (__v4di a, __v4di b, __v4di c)
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{
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return a < 0 ? b : c;
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}
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__attribute__((noipa)) __v4di
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f6 (__v4di a, __v4di b, __v4di c)
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{
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return a >= 0 ? b : c;
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}
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__attribute__((noipa)) __v8sf
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f7 (__v8si a, __v8sf b, __v8sf c)
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{
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return a < 0 ? b : c;
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}
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__attribute__((noipa)) __v8sf
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f8 (__v8si a, __v8sf b, __v8sf c)
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{
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return a >= 0 ? b : c;
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}
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__attribute__((noipa)) __v4df
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f9 (__v4di a, __v4df b, __v4df c)
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{
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return a < 0 ? b : c;
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}
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__attribute__((noipa)) __v4df
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f10 (__v4di a, __v4df b, __v4df c)
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{
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return a >= 0 ? b : c;
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}
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@ -0,0 +1,72 @@
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/* PR target/54700 */
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/* { dg-do run { target avx2 } } */
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/* { dg-options "-O2 -std=c++14 -mavx2 -mno-xop -mno-avx512f" } */
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#include "avx2-check.h"
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#define TEST avx2_test
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#include "avx2-pr54700-1.C"
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static void
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TEST ()
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{
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__v32qi v32qia = { -128, 12, -1, 127, 115, 0, -19, 125, -125, 12, 0, -37, 37, 15, 98, -105,
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0, 1, 2, 3, -1, -2, -3, -4, 4, -5, 5, -6, 6, -7, 7, -8 };
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__v32qi v32qib = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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-1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16 };
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__v32qi v32qic = { 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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-17, -18, -19, -20, -21, -22, -23, -24, -25, -26, -27, -28, -29, -30, -31, -32 };
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__v32qi v32qie = { 1, 18, 3, 20, 21, 22, 7, 24, 9, 26, 27, 12, 29, 30, 31, 16,
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-17, -18, -19, -20, -5, -6, -7, -8, -25, -10, -27, -12, -29, -14, -31, -16 };
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__v32qi v32qif = { 17, 2, 19, 4, 5, 6, 23, 8, 25, 10, 11, 28, 13, 14, 15, 32,
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-1, -2, -3, -4, -21, -22, -23, -24, -9, -26, -11, -28, -13, -30, -15, -32 };
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__v32qi v32qir = f1 (v32qia, v32qib, v32qic);
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if (__builtin_memcmp (&v32qir, &v32qie, sizeof (__v32qi)))
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__builtin_abort ();
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v32qir = f2 (v32qia, v32qib, v32qic);
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if (__builtin_memcmp (&v32qir, &v32qif, sizeof (__v32qi)))
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__builtin_abort ();
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__v8si v8sia = { __INT_MAX__, -__INT_MAX__ - 1, -32, 12, __INT_MAX__ - 2, -__INT_MAX__, 15, -1 };
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__v8si v8sib = { 1, 2, 3, 4, -1, -2, -3, -4 };
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__v8si v8sic = { 5, 6, 7, 8, -5, -6, -7, -8 };
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__v8si v8sie = { 5, 2, 3, 8, -5, -2, -7, -4 };
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__v8si v8sif = { 1, 6, 7, 4, -1, -6, -3, -8 };
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__v8si v8sir = f3 (v8sia, v8sib, v8sic);
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if (__builtin_memcmp (&v8sir, &v8sie, sizeof (__v8si)))
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__builtin_abort ();
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v8sir = f4 (v8sia, v8sib, v8sic);
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if (__builtin_memcmp (&v8sir, &v8sif, sizeof (__v8si)))
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__builtin_abort ();
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__v4di v4dia = { -__LONG_LONG_MAX__, 1000LL * __INT_MAX__, __LONG_LONG_MAX__, -2 };
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__v4di v4dib = { 1, 2, -1, -2 };
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__v4di v4dic = { 3, 4, -3, -4 };
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__v4di v4die = { 1, 4, -3, -2 };
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__v4di v4dif = { 3, 2, -1, -4 };
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__v4di v4dir = f5 (v4dia, v4dib, v4dic);
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if (__builtin_memcmp (&v4dir, &v4die, sizeof (__v4di)))
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__builtin_abort ();
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v4dir = f6 (v4dia, v4dib, v4dic);
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if (__builtin_memcmp (&v4dir, &v4dif, sizeof (__v4di)))
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__builtin_abort ();
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__v8sf v8sfb = { 1.0f, 2.0f, 3.0f, 4.0f, -1.0f, -2.0f, -3.0f, -4.0f };
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__v8sf v8sfc = { 5.0f, 6.0f, 7.0f, 8.0f, -5.0f, -6.0f, -7.0f, -8.0f };
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__v8sf v8sfe = { 5.0f, 2.0f, 3.0f, 8.0f, -5.0f, -2.0f, -7.0f, -4.0f };
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__v8sf v8sff = { 1.0f, 6.0f, 7.0f, 4.0f, -1.0f, -6.0f, -3.0f, -8.0f };
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__v8sf v8sfr = f7 (v8sia, v8sfb, v8sfc);
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if (__builtin_memcmp (&v8sfr, &v8sfe, sizeof (__v8sf)))
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__builtin_abort ();
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v8sfr = f8 (v8sia, v8sfb, v8sfc);
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if (__builtin_memcmp (&v8sfr, &v8sff, sizeof (__v8sf)))
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__builtin_abort ();
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__v4df v4dfb = { 1.0, 2.0, -1.0, -2.0 };
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__v4df v4dfc = { 3.0, 4.0, -3.0, -4.0 };
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__v4df v4dfe = { 1.0, 4.0, -3.0, -2.0 };
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__v4df v4dff = { 3.0, 2.0, -1.0, -4.0 };
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__v4df v4dfr = f9 (v4dia, v4dfb, v4dfc);
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if (__builtin_memcmp (&v4dfr, &v4dfe, sizeof (__v4df)))
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__builtin_abort ();
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v4dfr = f10 (v4dia, v4dfb, v4dfc);
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if (__builtin_memcmp (&v4dfr, &v4dff, sizeof (__v4df)))
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__builtin_abort ();
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||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../../gcc.target/i386/m128-check.h"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../../gcc.target/i386/m256-check.h"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../../gcc.target/i386/sse4_1-check.h"
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/* PR target/54700 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -std=c++14 -msse4 -mno-avx -mno-xop" } */
|
||||
/* { dg-final { scan-assembler-not "pcmpgt\[bdq]" } } */
|
||||
/* { dg-final { scan-assembler-times "pblendvb" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "blendvps" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "blendvpd" 4 } } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
__attribute__((noipa)) __v16qi
|
||||
f1 (__v16qi a, __v16qi b, __v16qi c)
|
||||
{
|
||||
return a < 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v16qi
|
||||
f2 (__v16qi a, __v16qi b, __v16qi c)
|
||||
{
|
||||
return a >= 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v4si
|
||||
f3 (__v4si a, __v4si b, __v4si c)
|
||||
{
|
||||
return a < 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v4si
|
||||
f4 (__v4si a, __v4si b, __v4si c)
|
||||
{
|
||||
return a >= 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v2di
|
||||
f5 (__v2di a, __v2di b, __v2di c)
|
||||
{
|
||||
return a < 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v2di
|
||||
f6 (__v2di a, __v2di b, __v2di c)
|
||||
{
|
||||
return a >= 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v4sf
|
||||
f7 (__v4si a, __v4sf b, __v4sf c)
|
||||
{
|
||||
return a < 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v4sf
|
||||
f8 (__v4si a, __v4sf b, __v4sf c)
|
||||
{
|
||||
return a >= 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v2df
|
||||
f9 (__v2di a, __v2df b, __v2df c)
|
||||
{
|
||||
return a < 0 ? b : c;
|
||||
}
|
||||
|
||||
__attribute__((noipa)) __v2df
|
||||
f10 (__v2di a, __v2df b, __v2df c)
|
||||
{
|
||||
return a >= 0 ? b : c;
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/* PR target/54700 */
|
||||
/* { dg-do run { target sse4 } } */
|
||||
/* { dg-options "-O2 -std=c++14 -msse4 -mno-avx -mno-xop" } */
|
||||
|
||||
#ifndef CHECK_H
|
||||
#define CHECK_H "sse4_1-check.h"
|
||||
#endif
|
||||
|
||||
#ifndef TEST
|
||||
#define TEST sse4_1_test
|
||||
#endif
|
||||
|
||||
#include CHECK_H
|
||||
|
||||
#include "sse4_1-pr54700-1.C"
|
||||
|
||||
static void
|
||||
TEST ()
|
||||
{
|
||||
__v16qi v16qia = { -128, 12, -1, 127, 115, 0, -19, 125, -125, 12, 0, -37, 37, 15, 98, -105 };
|
||||
__v16qi v16qib = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 };
|
||||
__v16qi v16qic = { 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 };
|
||||
__v16qi v16qie = { 1, 18, 3, 20, 21, 22, 7, 24, 9, 26, 27, 12, 29, 30, 31, 16 };
|
||||
__v16qi v16qif = { 17, 2, 19, 4, 5, 6, 23, 8, 25, 10, 11, 28, 13, 14, 15, 32 };
|
||||
__v16qi v16qir = f1 (v16qia, v16qib, v16qic);
|
||||
if (__builtin_memcmp (&v16qir, &v16qie, sizeof (__v16qi)))
|
||||
__builtin_abort ();
|
||||
v16qir = f2 (v16qia, v16qib, v16qic);
|
||||
if (__builtin_memcmp (&v16qir, &v16qif, sizeof (__v16qi)))
|
||||
__builtin_abort ();
|
||||
__v4si v4sia = { __INT_MAX__, -__INT_MAX__ - 1, -32, 12 };
|
||||
__v4si v4sib = { 1, 2, 3, 4 };
|
||||
__v4si v4sic = { 5, 6, 7, 8 };
|
||||
__v4si v4sie = { 5, 2, 3, 8 };
|
||||
__v4si v4sif = { 1, 6, 7, 4 };
|
||||
__v4si v4sir = f3 (v4sia, v4sib, v4sic);
|
||||
if (__builtin_memcmp (&v4sir, &v4sie, sizeof (__v4si)))
|
||||
__builtin_abort ();
|
||||
v4sir = f4 (v4sia, v4sib, v4sic);
|
||||
if (__builtin_memcmp (&v4sir, &v4sif, sizeof (__v4si)))
|
||||
__builtin_abort ();
|
||||
__v2di v2dia = { -__LONG_LONG_MAX__, 1000LL * __INT_MAX__ };
|
||||
__v2di v2dib = { 1, 2 };
|
||||
__v2di v2dic = { 3, 4 };
|
||||
__v2di v2die = { 1, 4 };
|
||||
__v2di v2dif = { 3, 2 };
|
||||
__v2di v2dir = f5 (v2dia, v2dib, v2dic);
|
||||
if (__builtin_memcmp (&v2dir, &v2die, sizeof (__v2di)))
|
||||
__builtin_abort ();
|
||||
v2dir = f6 (v2dia, v2dib, v2dic);
|
||||
if (__builtin_memcmp (&v2dir, &v2dif, sizeof (__v2di)))
|
||||
__builtin_abort ();
|
||||
__v4sf v4sfb = { 1.0f, 2.0f, 3.0f, 4.0f };
|
||||
__v4sf v4sfc = { 5.0f, 6.0f, 7.0f, 8.0f };
|
||||
__v4sf v4sfe = { 5.0f, 2.0f, 3.0f, 8.0f };
|
||||
__v4sf v4sff = { 1.0f, 6.0f, 7.0f, 4.0f };
|
||||
__v4sf v4sfr = f7 (v4sia, v4sfb, v4sfc);
|
||||
if (__builtin_memcmp (&v4sfr, &v4sfe, sizeof (__v4sf)))
|
||||
__builtin_abort ();
|
||||
v4sfr = f8 (v4sia, v4sfb, v4sfc);
|
||||
if (__builtin_memcmp (&v4sfr, &v4sff, sizeof (__v4sf)))
|
||||
__builtin_abort ();
|
||||
__v2df v2dfb = { 1.0, 2.0 };
|
||||
__v2df v2dfc = { 3.0, 4.0 };
|
||||
__v2df v2dfe = { 1.0, 4.0 };
|
||||
__v2df v2dff = { 3.0, 2.0 };
|
||||
__v2df v2dfr = f9 (v2dia, v2dfb, v2dfc);
|
||||
if (__builtin_memcmp (&v2dfr, &v2dfe, sizeof (__v2df)))
|
||||
__builtin_abort ();
|
||||
v2dfr = f10 (v2dia, v2dfb, v2dfc);
|
||||
if (__builtin_memcmp (&v2dfr, &v2dff, sizeof (__v2df)))
|
||||
__builtin_abort ();
|
||||
}
|
||||
Loading…
Reference in New Issue