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re PR target/68917 (test suite failure for builtin-bitops-1.c)

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PR target/68917
	* config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of
	SI values.  Explicitly convert SI to DI and vice-versa.

From-SVN: r232028
This commit is contained in:
Bernd Edlinger 2016-01-01 18:45:41 +00:00 committed by Bernd Edlinger
parent 2f9686033d
commit fecd16d238
2 changed files with 13 additions and 4 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2016-01-01 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR target/68917
* config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of
SI values. Explicitly convert SI to DI and vice-versa.
2016-01-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/69070

11
gcc/config/tilegx/tilegx.md
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@ -1799,13 +1799,16 @@
(define_expand "clzsi2"
[(set (match_dup 2)
(ashift:DI (match_operand:SI 1 "reg_or_0_operand" "")
(zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" "")))
(set (match_dup 2)
(ashift:DI (match_dup 2)
(const_int 32)))
(set (subreg:DI (match_operand:SI 0 "register_operand" "") 0)
(clz:DI (match_dup 2)))]
(set (match_dup 2)
(clz:DI (match_dup 2)))
(set (match_operand:SI 0 "register_operand" "")
(subreg:SI (match_dup 2) 0))]
""
{
operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);
operands[2] = gen_reg_rtx (DImode);
})