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[AArch64] Rename the internal "Upl" constraint

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The SVE port uses the public constraints "Upl" and "Upa" to mean
"low predicate register" and "any predicate register" respectively.
"Upl" was already used as an internal-only constraint by the
addition patterns, so this patch renames it to "Uaa" ("two adds
needed").

2017-11-01  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/constraints.md (Upl): Rename to...
	(Uaa): ...this.
	* config/aarch64/aarch64.md
	(*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
	Update accordingly.

Reviewed-By: James Greenhalgh  <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254326
This commit is contained in:
Richard Sandiford 2017-11-01 20:47:28 +00:00 committed by Richard Sandiford
parent 0100c5f9b7
commit ff1335e208
3 changed files with 13 additions and 3 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2017-11-01 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* config/aarch64/constraints.md (Upl): Rename to...
(Uaa): ...this.
* config/aarch64/aarch64.md
(*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
Update accordingly.
2017-11-01 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>

4
gcc/config/aarch64/aarch64.md
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@ -1562,7 +1562,7 @@
(match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r")
(plus:GPI
(match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk")
(match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))]
(match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))]
""
"@
add\\t%<w>0, %<w>1, %2
@ -1580,7 +1580,7 @@
(match_operand:DI 0 "register_operand" "=rk,rk,rk,r")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk")
(match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))]
(match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))]
""
"@
add\\t%w0, %w1, %2

2
gcc/config/aarch64/constraints.md
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@ -35,7 +35,7 @@
(and (match_code "const_int")
(match_test "aarch64_uimm12_shift (ival)")))
(define_constraint "Upl"
(define_constraint "Uaa"
"@internal A constant that matches two uses of add instructions."
(and (match_code "const_int")
(match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))